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Fri, 09 May 2025 03:29:42 -0700 (PDT) Message-ID: <869269a7-8267-45f3-9e4d-678de18c0888@tuxon.dev> Date: Fri, 9 May 2025 13:29:40 +0300 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/8] PCI: rzg3s-host: Add Initial PCIe Host Driver for Renesas RZ/G3S SoC From: Claudiu Beznea To: Bjorn Helgaas Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, saravanak@google.com, p.zabel@pengutronix.de, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea References: <20250501201211.GA768334@bhelgaas> <26bdfbd6-7bf5-4688-b793-5d0f613d340b@tuxon.dev> Content-Language: en-US In-Reply-To: <26bdfbd6-7bf5-4688-b793-5d0f613d340b@tuxon.dev> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, Bjorn, On 05.05.2025 14:26, Claudiu Beznea wrote: > Hi, Bjorn, > > On 01.05.2025 23:12, Bjorn Helgaas wrote: >> On Wed, Apr 30, 2025 at 01:32:33PM +0300, Claudiu wrote: >>> From: Claudiu Beznea >>> >>> The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express >>> Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions >>> only as a root complex, with a single-lane (x1) configuration. The >>> controller includes Type 1 configuration registers, as well as IP >>> specific registers (called AXI registers) required for various adjustments. >>> >>> Other Renesas RZ SoCs (e.g., RZ/G3E, RZ/V2H) share the same AXI registers >>> but have both Root Complex and Endpoint capabilities. As a result, the PCIe >>> host driver can be reused for these variants with minimal adjustments. >> >> I guess this current driver only supports RZ/GS3 in Root Complex mode? > > That's right. > >> If so, I don't think this paragraph is necessary or really relevant. > > OK, I'll drop it. > >> >>> +++ b/drivers/pci/controller/pcie-rzg3s-host.c >>> @@ -0,0 +1,1561 @@ >> >> I can't figure out the line width you're using. Generally code in >> drivers/pci/ is formatted to fit in 80 columns. Much of this file is >> formatted for that, but there are many cases that seem to use 90 or >> 100 columns. > > I formated it at 100 columns where the lines were longer. I wasn't aware > the PCI rule is to have line formated at 80 columns. I'll switch to it in > the next version. > >> >> For single-line comments that are not a sentence or are a single >> sentence, it's typical to omit the period at end. > > I'll follow this rule, too. > >> >>> +static void rzg3s_pcie_update_bits(void __iomem *base, u32 offset, u32 mask, u32 val) >>> +{ >>> + u32 tmp; >>> + >>> + tmp = readl(base + offset); >>> + tmp &= ~mask; >>> + tmp |= val & mask; >>> + writel(tmp, base + offset); >>> +} >> >> Nothing rzg3s-specific here. >> >> I think u32p_replace_bits() (include/linux/bitfield.h) is basically this. > > I wasn't aware of it. I'll use it in the next version. Thank for pointing it. I look into changing to u32p_replace_bits() but this one needs a mask that can be verified at build time. It cannot be used directly in this function. Would you prefer me to replace all the calls to rzg3s_pcie_update_bits() with: tmp = readl(); u32p_replace_bits(&tmp, ...) writel(tmp); or is it OK for you to keep it as is? Thank you, Claudiu