Re: [PATCH v2 5/6] drm/panel: st7703: Drive XBD599 panel at higher clock rate

Jernej Škrabec
2024-02-05T17:59:15Z

Dne ponedeljek, 05. februar 2024 ob 16:22:28 CET je Frank Oltmanns napisal(a):
> This panel is used in the pinephone that runs on a Allwinner A64 SOC.
> The SOC requires pll-mipi to run at more than 500 MHz.
>
> This is the relevant clock tree:
> pll-mipi
> tcon0
> tcon-data-clock
>
> tcon-data-clock has to run at 1/4 the DSI per-lane bit rate. The XBD599
> has 24 bpp and 4 lanes. Therefore, the resulting requested
> tcon-data-clock rate is:
> crtc_clock * 1000 * (24 / 4) / 4
>
> tcon-data-clock runs at tcon0 / 4 (fixed divisor), so it requests a
> parent rate of
> 4 * (crtc_clock * 1000 * (24 / 4) / 4)
>
> Since tcon0 is a ccu_mux, the rate of tcon0 equals the rate of pll-mipi.
>
> pll-mipi's constraint to run at 500MHz or higher forces us to have a
> crtc_clock >= 83333 kHz if we want a 60 Hz vertical refresh rate.
>
> Change [hv]sync_(start|end) so that we reach a clock rate of 83502 kHz
> so that it is high enough to align with pll-pipi limits.

Typo: pll-pipi -> pll-mipi

Best regards,
Jernej

>
> Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
> ---
> drivers/gpu/drm/panel/panel-sitronix-st7703.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
> index b55bafd1a8be..6886fd7f765e 100644
> --- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
> +++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
> @@ -320,14 +320,14 @@ static int xbd599_init_sequence(struct st7703 *ctx)
>
> static const struct drm_display_mode xbd599_mode = {
> .hdisplay = 720,
> - .hsync_start = 720 + 40,
> - .hsync_end = 720 + 40 + 40,
> - .htotal = 720 + 40 + 40 + 40,
> + .hsync_start = 720 + 65,
> + .hsync_end = 720 + 65 + 65,
> + .htotal = 720 + 65 + 65 + 65,
> .vdisplay = 1440,
> - .vsync_start = 1440 + 18,
> - .vsync_end = 1440 + 18 + 10,
> - .vtotal = 1440 + 18 + 10 + 17,
> - .clock = 69000,
> + .vsync_start = 1440 + 30,
> + .vsync_end = 1440 + 30 + 22,
> + .vtotal = 1440 + 30 + 22 + 29,
> + .clock = (720 + 65 + 65 + 65) * (1440 + 30 + 22 + 29) * 60 / 1000,
> .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
> .width_mm = 68,
> .height_mm = 136,
>
>