From: Eric Anholt <eric@anholt.net>
To: Martin Sperl <kernel@martin.sperl.org>
Cc: Jonathan Corbet <corbet@lwn.net>,
Stephen Warren <swarren@wwwdotorg.org>,
Lee Jones <lee@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Rob Herring <robh+dt@kernel.org>,
linux-doc@vger.kernel.org, linux-rpi-kernel@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 2/8] clk: bcm2835: add missing PLL clock divider
Date: Thu, 17 Mar 2016 10:58:20 -0700 [thread overview]
Message-ID: <8737rpm1fn.fsf@eliezer.anholt.net> (raw)
In-Reply-To: <C5EA56E8-F1A1-453D-A421-3E29853F3127@martin.sperl.org>
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Martin Sperl <kernel@martin.sperl.org> writes:
>> On 17.03.2016, at 17:57, Eric Anholt <eric@anholt.net> wrote:
>>
>>
>> These don't exist on the hardware as far as I've been able to find. "I
>> found it in a header file somewhere" is not sufficient justification to
>> expose it.
>>
>> I'm working on getting a series of all of these reviewed and ready, so
>> I'm just dropping these PLLB hunks.
>
> Fine with that - my test shows that these are not configured by the firmware.
>
> As for headers: my experience is that these are the better resource
> compared to all the public available documentation…
>
> If you remember the “frac” bit discussion where you said:
>
> Once again, trusting the docs turns out to be a bad idea. You're right,
> the non-MASH clocks *do* have a bit 9 to enable fractional mode. Sigh.
>
> Also my understanding is that those headers are still used by the firmware
> developers, so I guess that these are pretty stable and well maintained
> (even if the ones available are by now a bit dated).
>
> They even contain ifdefs for some earlier versions of the chip -
> see the dma-channels and their interrupts…
> I.e: BCM2708A0 which does not have the DMA channels 9 to 15
>
> So I would not discount all those pieces of information as totally
> irrelevant.
I'm looking at the hardware source, and at the place where all the other
PLL dividers are, PLLB only has ARM.
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next prev parent reply other threads:[~2016-03-17 17:58 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-29 15:43 [PATCH 0/8] clk: bcm2835: add most missing clocks of bcm2835 kernel
2016-02-29 15:43 ` [PATCH 1/8] clk: bcm2835: documenentation: add graphiz bcm2835 clock tree kernel
2016-02-29 15:43 ` [PATCH 2/8] clk: bcm2835: add missing PLL clock divider kernel
2016-03-17 16:57 ` Eric Anholt
2016-03-17 17:38 ` Martin Sperl
2016-03-17 17:58 ` Eric Anholt [this message]
2016-02-29 15:43 ` [PATCH 3/8] clk: bcm2835: add missing osc and per clocks kernel
2016-03-17 17:10 ` Eric Anholt
2016-03-17 17:19 ` Eric Anholt
2016-02-29 15:43 ` [PATCH 4/8] clk: bcm2835: add the camera related clocks cam0, cam1 and ccp2 kernel
2016-02-29 15:43 ` [PATCH 5/8] clk: bcm2835: add the dsi clocks kernel
2016-03-17 17:27 ` Eric Anholt
2016-02-29 15:44 ` [PATCH 6/8] clk: bcm2835: add arm clock kernel
2016-02-29 15:44 ` [PATCH 7/8] clk: bcm2835: add gates that require PM_DEBUG to be set kernel
2016-02-29 15:44 ` [PATCH 8/8] clk: bcm2835: add the testdebug clock generators kernel
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