From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6634E2263A; Sun, 4 Aug 2024 09:53:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722765181; cv=none; b=Qqhw8AQKqt8rGKkSBGTBOrkIQoQsA8mSqIAt0TA5YWdl/tYsMYpH0pDxkvufNj8DKXw1f+PgQtmfxf46WC0neISF9v+HjNDLvwqfxaSuoM8wf49RijPMEnN/anpnn5FiquWDVR0MPyA5i1aIl3VSjk/Ra2cxtaLsRceKH4put0s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722765181; c=relaxed/simple; bh=2V4bwc4EGQDBu7h5327C3Wy4iLbvMzYSTOhrOTbqqMk=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=OJtTuM1Xb8W+GTXPnsANIzEdGWf5usWj0MPZArLeAO9umPcEoOHoD7g6oV/G00ntVgbCr8NdAU7YlO1IECBNv8iy4IpUtE/n/qXbis8UnvZ/nUoM492DP6wh8R3GioRdLbnDml4unRCL0vvrrsxy5cI8jR17AQSE3NRdvOtld4Y= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RzgD4cZW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RzgD4cZW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C80FBC32786; Sun, 4 Aug 2024 09:52:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722765180; bh=2V4bwc4EGQDBu7h5327C3Wy4iLbvMzYSTOhrOTbqqMk=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=RzgD4cZWYz7mqyo2JXz21QGjHm1HNNAaEQNcvSosSy4CkJzTIoN1lNIkvjGGZWgsB /1JGHQWAp78LwW3lmOz0DZukBAbiY5w/4my9ezBKf4wE+RdMwfPR+dsP5MD2v1zK52 k7O9cXyaeW80eKQy9qdJbsOyLjDDaUPdtULWUgzSOnBoheMGfic+a19LEIfWvKvvBD bgU1rGY+UA40ZxTJwldeXVpE1a+xU65r6loHw9fg/aApppm+k1LxktkgPTrKDjqREF NhPd9qMtwt2j/0wo+2wRkjaO9atvKSqlTjdgXQE6Jm49K9vC+BZv9cQAvm4/Lpk43U aPKGnzleb/4PA== Message-ID: <87503c5b-95dc-463b-8363-3e1fab03f8f2@kernel.org> Date: Sun, 4 Aug 2024 11:52:53 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] dt-bindings: clock: add rk3576 cru bindings To: Detlev Casanova , linux-kernel@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel , Elaine Zhang , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com References: <20240802214053.433493-1-detlev.casanova@collabora.com> <20240802214053.433493-2-detlev.casanova@collabora.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 02/08/2024 23:35, Detlev Casanova wrote: > Document the device tree bindings of the rockchip rk3576 SoC > clock and reset unit. > > Signed-off-by: Detlev Casanova A nit, subject: drop second/last, redundant "bindings". The "dt-bindings" prefix is already stating that these are bindings. See also: https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18 > --- > .../bindings/clock/rockchip,rk3576-cru.yaml | 73 +++++++++++++++++++ > 1 file changed, 73 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml > new file mode 100644 > index 0000000000000..929eb6183bf18 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml > @@ -0,0 +1,73 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip rk3576 Family Clock and Reset Control Module > + > +maintainers: > + - Elaine Zhang > + - Heiko Stuebner > + > +description: | > + The RK3576 clock controller generates the clock and also implements a reset > + controller for SoC peripherals. For example it provides SCLK_UART2 and > + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART > + module. > + Each clock is assigned an identifier and client nodes can use this identifier > + to specify the clock which they consume. All available clock and reset IDs > + are defined as preprocessor macros in dt-binding headers. Drop paragraph, it is obvious. You could provide here the name of the header... > + > +properties: > + compatible: > + enum: > + - rockchip,rk3576-cru > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + "#reset-cells": > + const: 1 > + > + clocks: > + minItems: 2 You can drop minitems > + maxItems: 2 > + > + clock-names: > + items: > + - const: xin24m > + - const: xin32k > + > + assigned-clocks: true > + > + assigned-clock-rates: true > + > + assigned-clock-parents: true Drop all these three > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > > + phandle to the syscon managing the "general register files". It is used > + for GRF muxes, if missing any muxes present in the GRF will not be > + available. > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - "#reset-cells" > + > +additionalProperties: false > + > +examples: > + - | > + cru: clock-controller@27200000 { Drop unused label > + compatible = "rockchip,rk3576-cru"; > + reg = <0xfd7c0000 0x5c000>; > + #clock-cells = <1>; > + #reset-cells = <1>; Make the example complete. > + }; Best regards, Krzysztof