From: Gregory CLEMENT <gregory.clement@free-electrons.com>
To: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Andrew Lunn <andrew@lunn.ch>, Jason Cooper <jason@lakedaemon.net>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH v2 1/3] dt-bindings: add Marvell core PLL and clock divider PMU documentation
Date: Mon, 07 Dec 2015 18:37:47 +0100 [thread overview]
Message-ID: <87oae2b1n8.fsf@free-electrons.com> (raw)
In-Reply-To: <E1a5ijC-0007pd-SL@rmk-PC.arm.linux.org.uk> (Russell King's message of "Sun, 06 Dec 2015 23:28:26 +0000")
Hi Russell,
On lun., déc. 07 2015, Russell King <rmk+kernel@arm.linux.org.uk> wrote:
> Add documentation for the Marvell clock divider driver, which is used
> to source clocks for the AXI bus, video decoder, GPU and LCD blocks.
>
> Acked-by: Andrew Lunn <andrew@lunn.ch>
> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Applied on mvebu/dt
Thanks,
Gregory
> ---
> .../bindings/clock/dove-divider-clock.txt | 28 ++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/dove-divider-clock.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/dove-divider-clock.txt b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt
> new file mode 100644
> index 000000000000..e3eb0f657c5e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/dove-divider-clock.txt
> @@ -0,0 +1,28 @@
> +PLL divider based Dove clocks
> +
> +Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
> +high speed clocks for a number of peripherals. These dividers are part of
> +the PMU, and thus this node should be a child of the PMU node.
> +
> +The following clocks are provided:
> +
> +ID Clock
> +-------------
> +0 AXI bus clock
> +1 GPU clock
> +2 VMeta clock
> +3 LCD clock
> +
> +Required properties:
> +- compatible : shall be "marvell,dove-divider-clock"
> +- reg : shall be the register address of the Core PLL and Clock Divider
> + Control 0 register. This will cover that register, as well as the
> + Core PLL and Clock Divider Control 1 register. Thus, it will have
> + a size of 8.
> +- #clock-cells : from common clock binding; shall be set to 1
> +
> +divider_clk: core-clock@0064 {
> + compatible = "marvell,dove-divider-clock";
> + reg = <0x0064 0x8>;
> + #clock-cells = <1>;
> +};
> --
> 2.1.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
prev parent reply other threads:[~2015-12-07 17:37 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-06 23:28 [PATCH v2 1/3] dt-bindings: add Marvell core PLL and clock divider PMU documentation Russell King
2015-12-07 17:37 ` Gregory CLEMENT [this message]
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