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Mon, 10 Nov 2025 15:19:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1762784365; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=AixT7Oh+5FxWWMEZrxu1kDjvQPH8JSRwqc8kK2kvJaU=; b=tGk9KTsQI2Q65bzJrFFGVZMBlqJL0S5t7NCc7oHdD3VkJ7+4DvdWCQ1H+fAUPwNSCCkKTo mb4cak229bqD5R2nYdIofNZNfCwEYFNwjrDP2XMzY4gRkKtvgxHNNDrEpzrh+F7s+3tohi IF88La9EBzOBGWNmzeDbgNfVvwUMISSod2H02ulMO04OGgjoqPISyStUXuj5kb6RpzzPfx u3G2MpuRo2y5hlF0j1NqsgamhemSCsrxPqK4Z/TgsRHzg6He2ENBbGaz16F4XH62zhf7nz ypVF6xKKeHJphkB1yWfga+Le2zF3iBCyw2R7QXAhmJKB/9bIEv/riz+QGqXDXQ== From: Gregory CLEMENT To: Josua Mayer , Andrew Lunn , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd Cc: Rabeeh Khoury , Yazan Shhady , Mikhail Anikin , Jon Nettleton , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Josua Mayer Subject: Re: [PATCH 1/2] Revert "arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports" In-Reply-To: <20251030-cn913x-pci-clk-v1-1-e034d5903df1@solid-run.com> References: <20251030-cn913x-pci-clk-v1-0-e034d5903df1@solid-run.com> <20251030-cn913x-pci-clk-v1-1-e034d5903df1@solid-run.com> Date: Mon, 10 Nov 2025 15:19:23 +0100 Message-ID: <87pl9qrmvo.fsf@BLaptop.bootlin.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Josua Mayer writes: > This reverts commit 794a066688038df46c01e177cc6faebded0acba4 because it > misunderstood interworking between arm trusted firmware and the common > phy driver, and does not consistently resolve the issue it was intended > to address. > > Further diagnostics have revealed the root cause for the reported system > lock-up in a race condition between pci driver probe and clock core > disabling unused clocks. > > Revert the wrong change restoring driver control over all pci lanes. > As a temporary workaround for the original issue, users can boot with > "clk_ignore_unused". > > Signed-off-by: Josua Mayer Applied on mvebu/dt64 Thanks, Gregory > --- > arch/arm64/boot/dts/marvell/cn9132-clearfog.dts | 16 ++-------------- > 1 file changed, 2 insertions(+), 14 deletions(-) > > diff --git a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts b/arch/arm64= /boot/dts/marvell/cn9132-clearfog.dts > index 5cf83d8ca1f59..2507896d58f9b 100644 > --- a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts > +++ b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts > @@ -413,13 +413,7 @@ fixed-link { > /* SRDS #0,#1,#2,#3 - PCIe */ > &cp0_pcie0 { > num-lanes =3D <4>; > - /* > - * The mvebu-comphy driver does not currently know how to pass correct > - * lane-count to ATF while configuring the serdes lanes. > - * Rely on bootloader configuration only. > - * > - * phys =3D <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0= _comphy3 0>; > - */ > + phys =3D <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_co= mphy3 0>; > status =3D "okay"; > }; >=20=20 > @@ -481,13 +475,7 @@ &cp1_eth0 { > /* SRDS #0,#1 - PCIe */ > &cp1_pcie0 { > num-lanes =3D <2>; > - /* > - * The mvebu-comphy driver does not currently know how to pass correct > - * lane-count to ATF while configuring the serdes lanes. > - * Rely on bootloader configuration only. > - * > - * phys =3D <&cp1_comphy0 0>, <&cp1_comphy1 0>; > - */ > + phys =3D <&cp1_comphy0 0>, <&cp1_comphy1 0>; > status =3D "okay"; > }; >=20=20 > > --=20 > 2.51.0 > --=20 Gr=C3=A9gory CLEMENT, Bootlin Embedded Linux and Kernel engineering https://bootlin.com