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From: Eric Anholt <eric@anholt.net>
To: Boris Brezillon <boris.brezillon@bootlin.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Ray Jui <rjui@broadcom.com>,
	Scott Branden <sbranden@broadcom.com>,
	bcm-kernel-feedback-list@broadcom.com,
	Stephen Warren <swarren@wwwdotorg.org>,
	Lee Jones <lee@kernel.org>,
	linux-rpi-kernel@lists.infradead.org,
	Mike Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	linux-clk@vger.kernel.org
Cc: Boris Brezillon <boris.brezillon@bootlin.com>, stable@vger.kernel.org
Subject: Re: [PATCH 3/4] clk: bcm2835: De-assert/assert PLL reset signal when appropriate
Date: Thu, 08 Feb 2018 15:15:42 +0000	[thread overview]
Message-ID: <87po5f5x7l.fsf@anholt.net> (raw)
In-Reply-To: <20180208134338.24590-3-boris.brezillon@bootlin.com>

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Boris Brezillon <boris.brezillon@bootlin.com> writes:

> In order to enable a PLL, not only the PLL has to be powered up and
> locked, but you also have to de-assert the reset signal. The last part
> was missing. Add it so PLLs that were not enabled by the FW/bootloader
> can be enabled from Linux.
>
> Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
> ---
>  drivers/clk/bcm/clk-bcm2835.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index a07f6451694a..6c5d4a8e426c 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -602,6 +602,9 @@ static void bcm2835_pll_off(struct clk_hw *hw)
>  	const struct bcm2835_pll_data *data = pll->data;
>  
>  	spin_lock(&cprman->regs_lock);
> +	cprman_write(cprman, data->a2w_ctrl_reg,
> +		     cprman_read(cprman, data->a2w_ctrl_reg) &
> +		     ~A2W_PLL_CTRL_PRST_DISABLE);
>  	cprman_write(cprman, data->cm_ctrl_reg,
>  		     cprman_read(cprman, data->cm_ctrl_reg) |
>  		     CM_PLL_ANARST);

For turning off, the FW just does the equivalent of:

	cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
	cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN);

How about we do that, instead?

> @@ -640,6 +643,10 @@ static int bcm2835_pll_on(struct clk_hw *hw)
>  		cpu_relax();
>  	}
>  
> +	cprman_write(cprman, data->a2w_ctrl_reg,
> +		     cprman_read(cprman, data->a2w_ctrl_reg) |
> +		     A2W_PLL_CTRL_PRST_DISABLE);
> +
>  	return 0;
>  }

I agree with this hunk -- they drop PRST at the very end, after lock.

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  reply	other threads:[~2018-02-08 15:15 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-08 13:43 [PATCH 1/4] clk: bcm2835: Fix ana->maskX definitions Boris Brezillon
2018-02-08 13:43 ` [PATCH 2/4] clk: bcm2835: Protect sections updating shared registers Boris Brezillon
2018-02-08 15:14   ` Eric Anholt
2018-02-09  9:34   ` Eric Anholt
2018-03-19 16:29   ` Stephen Boyd
2018-02-08 13:43 ` [PATCH 3/4] clk: bcm2835: De-assert/assert PLL reset signal when appropriate Boris Brezillon
2018-02-08 15:15   ` Eric Anholt [this message]
2018-02-08 17:49     ` Boris Brezillon
2018-02-14 10:37     ` Boris Brezillon
2018-02-22 20:18       ` Eric Anholt
2018-02-08 13:43 ` [PATCH 4/4] clk: bcm2835: Make sure the PLL is gated before changing its rate Boris Brezillon
2018-02-08 15:20   ` Eric Anholt
2018-02-08 17:56     ` Boris Brezillon
2018-02-09  9:32       ` Eric Anholt
2018-02-12  9:27         ` Boris Brezillon
2018-03-12 21:21           ` Stephen Boyd
2018-03-13 16:56             ` Eric Anholt
2018-03-19 16:26               ` Stephen Boyd
2018-03-22  9:13             ` Boris Brezillon
2018-03-22 16:38               ` Eric Anholt
2018-03-19 16:29 ` [PATCH 1/4] clk: bcm2835: Fix ana->maskX definitions Stephen Boyd

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