From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Stephen Boyd <sboyd@kernel.org>, mturquette@baylibre.com
Cc: matthias.bgg@gmail.com, wenst@chromium.org,
miles.chen@mediatek.com, chun-jie.chen@mediatek.com,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
rex-bc.chen@mediatek.com
Subject: Re: [PATCH] clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent
Date: Thu, 16 Jun 2022 10:48:44 +0200 [thread overview]
Message-ID: <88be9f00-2b1a-977d-dadd-95a131bf7f1f@collabora.com> (raw)
In-Reply-To: <20220616024442.1337EC3411E@smtp.kernel.org>
Il 16/06/22 04:44, Stephen Boyd ha scritto:
> Quoting AngeloGioacchino Del Regno (2022-06-14 02:10:20)
>> Add the CLK_SET_RATE_PARENT flag to the CLK_VDO0_DP_INTF0_DP_INTF
>> clock: this is required to trigger clock source selection on
>> CLK_TOP_EDP, while avoiding to manage the enablement of the former
>> separately from the latter in the displayport driver.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>
> Any Fixes tag?
Backporting is useless because there's no DisplayPort driver that supports MT8195
in the previous kernel versions, so this clock (and whatever logic behind it) is
unused.
Though, if you think that's going to be useful in any way, I can add one?
Regards,
Angelo
next prev parent reply other threads:[~2022-06-16 8:50 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-14 9:10 [PATCH] clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent AngeloGioacchino Del Regno
2022-06-16 2:44 ` Stephen Boyd
2022-06-16 8:48 ` AngeloGioacchino Del Regno [this message]
2022-06-17 0:11 ` Stephen Boyd
2022-06-16 7:12 ` Rex-BC Chen
2022-06-16 8:51 ` AngeloGioacchino Del Regno
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