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Fri, 09 May 2025 03:58:38 -0700 (PDT) Message-ID: <8a14cf38-9a7b-462b-80d1-ec5026b5a565@tuxon.dev> Date: Fri, 9 May 2025 13:58:37 +0300 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/7] clk: renesas: rzg2l-cpg: Add support for MSTOP in clock enable/disable API To: Geert Uytterhoeven Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea References: <20250410140628.4124896-1-claudiu.beznea.uj@bp.renesas.com> <20250410140628.4124896-4-claudiu.beznea.uj@bp.renesas.com> From: Claudiu Beznea Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, Geert, On 07.05.2025 18:47, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Thu, 10 Apr 2025 at 16:06, Claudiu wrote: >> From: Claudiu Beznea >> >> The RZ/{G2L, V2L, G3S} CPG versions support a feature called MSTOP. Each >> module has one or more MSTOP bits associated with it, and these bits need >> to be configured along with the module clocks. Setting the MSTOP bits >> switches the module between normal and standby states. >> >> Previously, MSTOP support was abstracted through power domains >> (struct generic_pm_domain::{power_on, power_off} APIs). With this >> abstraction, the order of setting the MSTOP and CLKON bits was as follows: >> >> Previous Order: >> A/ Switching to Normal State (e.g., during probe): >> 1/ Clear module MSTOP bits >> 2/ Set module CLKON bits >> >> B/ Switching to Standby State (e.g., during remove): >> 1/ Clear CLKON bits >> 2/ Set MSTOP bits >> >> However, in some cases (when the clock is disabled through devres), the >> order may have been (due to the issue described in link section): >> >> 1/ Set MSTOP bits >> 2/ Clear CLKON bits >> >> Recently, the hardware team has suggested that the correct order to set >> the MSTOP and CLKON bits is: >> >> Updated Order: >> A/ Switching to Normal State (e.g., during probe): >> 1/ Set CLKON bits >> 2/ Clear MSTOP bits > > What is the recommended order in case multiple clocks map to > the same module? Clear the MSTOP bit(s) after enabling the first clock, > or clear the MSTOP bit(s) after enabling all clocks? I can't find anything about this in the HW manual. > I believe the code implements the former? The proposed implementation clears the MSTOP after enabling the first clock taking into account that there might be cases where 2 clocks sharing the same MSTOP may not be both enabled for a particular functionality. Thank you for your review, Claudiu