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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d0aa492772sm4979595ad.42.2026.08.04.04.03.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Aug 2026 04:03:10 -0700 (PDT) Message-ID: <8af46926-fecc-4396-973e-2290ae285998@oss.qualcomm.com> Date: Tue, 4 Aug 2026 19:03:06 +0800 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: ipq-cmn-pll: keep the CMN block bus clocks enabled To: Stanislaw Pal Cc: Bjorn Andersson , Stephen Boyd , Michael Turquette , Mieczyslaw Nalewaj , Brian Masney , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20260730191353.557494-1-kuncy7@gmail.com> <20260803091003.15285-1-kuncy7@gmail.com> Content-Language: en-US From: Jie Luo In-Reply-To: <20260803091003.15285-1-kuncy7@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: czJMOVebhhZaSFCz1l5hmdyESRan9dpr X-Authority-Analysis: v=2.4 cv=SJRykuvH c=1 sm=1 tr=0 ts=6a71c6f1 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=DPF5wdA_JBoVcR1QEgUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: czJMOVebhhZaSFCz1l5hmdyESRan9dpr X-Proofpoint-Spam-Info: AW1haW4tMjYwODA0MDA4NyBTYWx0ZWRfX61hDmKDEuFIy dO/pMF+NKW3qwiK7dz+P8ZWRb/X75DkvnGHeeKFJb8AghTvfcu8p+zYhDfJNQScIQmqfLATs7C3 3dM73m+dmTvV/4i8ZQkkLcHDamSLk5c= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA0MDA4NyBTYWx0ZWRfXxT0jLbN10rTw zUgtD0VjuQ8KQwpt/uaDHzD0uNi1utVkQWWs7wUCCuVtofq7PWI5EqRO2bvTmg/sdwCRQQZ6vFw V9sehQf4giRtL+GVF50ApE7/Y1XG3/HGS9VbbUJ7TnKyo17QV3DNRwqZkLw2WFdaye6nP1kHas1 rXF+H/4Lm/eK445MYmCTyZLkztiImSp+VvkTXUdXXbSUzQ0TGwlu1WToFuY/VLhvuQ7u2IqoJ/D nHgQVhDag5dkRtUT6QCoZP0FnQ2hmaxCyX9adUNgHI482MWgrOM0GGz2t60HiSTKDFPaxTOryTi HULf0Pk/EXaaGcivP3a+9V21kS7xVbNJZ1K0nMqq2HGh7hjwEA59gsKFiTlQwYQ4kgCIS3lTdz/ btYkrfkv0UN2B+MP+vxFQK0VVxHK6uxl9LNfbLjUPDKV8mSvXJOjQm68MYLgGXJWL3ZNUF72ubO F4I+G+2vTCBsbaUHZyQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-04_02,2026-08-03_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 bulkscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608040087 On 8/3/2026 5:10 PM, Stanislaw Pal wrote: >> The CMN PLL AHB/SYS clocks will remain enabled as long as a downstream >> consumer of the CMN PLL clocks is active — this behaviour was confirmed >> experimentally on the IPQ9574 platform as example. > That is exactly the mechanism - and it is exactly what IPQ5018 does not > have. On IPQ9574 the nsscc node consumes the CMN PLL outputs in DT: > > ipq9574.dtsi: > nsscc: clock-controller@39b00000 { > clocks = <&xo_board_clk>, > <&cmn_pll NSS_1200MHZ_CLK>, > <&cmn_pll PPE_353MHZ_CLK>, ... > > so the device link holds the supplier active, which is what your > insmod/devmem experiment shows. > > On IPQ5018 there is no such consumer: nothing in ipq5018.dtsi references > any cmn_pll output clock - the only occurrences of the phandle are the > provider node itself and its own assigned-clocks. The actual users of > the CMN outputs on this SoC (the internal GE PHY and the uniphy blocks) > take them directly in hardware, with no DT linkage, so no device link > ever holds the provider active. A few ms after probe the autosuspend > gates the AHB/SYS clocks, and the box dies on the next bus access - > which is the measured behaviour the patch description quotes. The CMN PLL output clocks do not depend on the AHB or SYS clocks. They continue to operate correctly at the fixed rates even when the AHB and SYS clocks are disabled. Therefore, once the CMN PLL module is loaded, its output clocks are expected to operate at the correct frequencies. The downstream consumer is used to keep the AHB and SYS clocks enabled, allowing the CMN PLL registers to be accessed.