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bh=ahz7Bk3xD2P4hB8w3yAV0ESZON1h7UZOAAG/Qh3s/cc=; b=gIA9WO/EVlo/3W/T9UMgzqjOeDI+YlwQvejGmSx8OiqBcsRYMr82fW9JWGWUQbt+D++ehx i0BiixjDD/tLHqIuykHEQquKcuzys+/Nzk/+qHOjd6B+hJveADkXYRbe27+lwG4uVzClAb wuOwwldKKh1jNabsGDN9ia1+FRtHZaw= Message-ID: <8cd9693d-9ec0-4173-bcca-786915b5c4cc@ixit.cz> Date: Thu, 9 Apr 2026 22:38:15 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] arm64: dts: qcom: sdm845: Add missing MDSS reset To: Dmitry Baryshkov , Konrad Dybcio Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Ulf Hansson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20260217-sdm845-hdk-v1-0-866f1965fef7@oss.qualcomm.com> <20260217-sdm845-hdk-v1-3-866f1965fef7@oss.qualcomm.com> <590f75c2-6418-4d39-ba7e-589acdf98786@oss.qualcomm.com> <9405b67b-9e08-472d-a937-38c038fdf73a@oss.qualcomm.com> <9b4cb352-d1ed-402d-a55d-cce2d2fe1eed@oss.qualcomm.com> Content-Language: en-US From: David Heidelberg Autocrypt: addr=david@ixit.cz; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 18/02/2026 16:59, Dmitry Baryshkov wrote: > On Wed, Feb 18, 2026 at 03:28:01PM +0100, Konrad Dybcio wrote: >> >> >> On 18-Feb-26 12:58, Dmitry Baryshkov wrote: >>> On Wed, Feb 18, 2026 at 12:24:26PM +0100, Konrad Dybcio wrote: >>>> On 2/18/26 12:18 PM, David Heidelberg wrote: >>>>> On 18/02/2026 11:30, Konrad Dybcio wrote: >>>>>> On 2/17/26 10:20 PM, Dmitry Baryshkov wrote: >>>>>>> From: David Heidelberg >>>>>>> >>>>>>> If the OS does not support recovering the state left by the >>>>>>> bootloader it needs a way to reset display hardware, so that it can >>>>>>> start from a clean state. Add a reference to the relevant reset. >>>>>> >>>>>> This is not the relevant reset >>>>>> >>>>>> You want MDSS_CORE_BCR @ 0xaf0_2000 >>>>> >>>>> Thanks, I prepared the fixes [1]. >>>>> >>>>> I'll try to test it if it's not breaking anything for us and send as v2 of [2]. >>>>> >>>>> David >>>>> >>>>> [1] https://codeberg.org/sdm845/linux/commits/branch/b4/mdss-reset >>>>> [2] https://patchwork.kernel.org/project/linux-arm-msm/patch/20260112-mdss-reset-v1-1-af7c572204d3@ixit.cz/ >>>> >>>> Please don't alter the contents of dt-bindings, it really doesn't matter >>>> if on sdm845 it's reset0 or reset1, that's why we define them in the first >>>> place >>> >>> I dpn't think that will pass. Current reset is defined as RSCC, we can't >>> change that to CORE behind the scene. I'd prefer David's approach. >> >> Back when I replied, David had a patch that removed the current RSCC >> reset definition in dt-bindings (at index 0) and re-used that index >> for CORE, putting RSCC at index 1. Perhaps it's better to link to >> specific commits when making comments, note to self :P > > Yes, I saw the commit having two resets. Anyway, as we saw, it doesn't > work. So, finally I spent "so much effort" (read throwing it at LLM) looking at: arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x9d4bb500, fsynr=0x170021, cbfrsynra=0xc88, cb=11 arm-smmu 15000000.iommu: FSR = 00000402 [Format=2 TF], SID=0xc88 arm-smmu 15000000.iommu: FSYNR0 = 00170021 [S1CBNDX=23 PNU PLVL=1] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x9d4c6900, fsynr=0x170021, cbfrsynra=0x880, cb=11 arm-smmu 15000000.iommu: FSR = 00000402 [Format=2 TF], SID=0x880 arm-smmu 15000000.iommu: FSYNR0 = 00170021 [S1CBNDX=23 PNU PLVL=1] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x9d4c3f00, fsynr=0x170021, cbfrsynra=0xc88, cb=11 arm-smmu 15000000.iommu: FSR = 00000402 [Format=2 TF], SID=0xc88 arm-smmu 15000000.iommu: FSYNR0 = 00170021 [S1CBNDX=23 PNU PLVL=1] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x9d4cff00, fsynr=0x170021, cbfrsynra=0xc88, cb=11 arm-smmu 15000000.iommu: FSR = 00000402 [Format=2 TF], SID=0xc88 arm-smmu 15000000.iommu: FSYNR0 = 00170021 [S1CBNDX=23 PNU PLVL=1] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x9d4cd220, fsynr=0x170021, cbfrsynra=0x880, cb=11 arm-smmu 15000000.iommu: FSR = 00000402 [Format=2 TF], SID=0x880 arm-smmu 15000000.iommu: FSYNR0 = 00170021 [S1CBNDX=23 PNU PLVL=1] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x9d4d9a00, fsynr=0x170021, cbfrsynra=0x880, cb=11 arm-smmu 15000000.iommu: FSR = 00000402 [Format=2 TF], SID=0x880 arm-smmu 15000000.iommu: FSYNR0 = 00170021 [S1CBNDX=23 PNU PLVL=1] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x9d4deb00, fsynr=0x170021, cbfrsynra=0x880, cb=11 arm-smmu 15000000.iommu: FSR = 00000402 [Format=2 TF], SID=0x880 arm-smmu 15000000.iommu: FSYNR0 = 00170021 [S1CBNDX=23 PNU PLVL=1] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x9d4e3400, fsynr=0x170021, cbfrsynra=0xc88, cb=11 arm-smmu 15000000.iommu: FSR = 00000402 [Format=2 TF], SID=0xc88 arm-smmu 15000000.iommu: FSYNR0 = 00170021 [S1CBNDX=23 PNU PLVL=1] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x9d4e9500, fsynr=0x170021, cbfrsynra=0xc88, cb=11 arm-smmu 15000000.iommu: FSR = 00000402 [Format=2 TF], SID=0xc88 arm-smmu 15000000.iommu: FSYNR0 = 00170021 [S1CBNDX=23 PNU PLVL=1] arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0x9d4eca00, fsynr=0x170021, cbfrsynra=0x880, cb=11 arm-smmu 15000000.iommu: FSR = 00000402 [Format=2 TF], SID=0x880 arm-smmu 15000000.iommu: FSYNR0 = 00170021 [S1CBNDX=23 PNU PLVL=1] These (or very similar warnings) are around sdm845 definitely 6.19+ / linux-next kernels for some time, but pretty harmless. LLM suggested multiple fixes, but when presenting possibility of implementing mdss reset it found it as most preferable [1]. Adding MDSS reset would most likely solve it. It's not critical, but not nice to see many red lines in the dmesg. Is there something I could experiment with to get closer to have proper MDSS reset? David [1] https://paste.sr.ht/~okias/c20e8bb1a67ba09df558d56da84894d71ddc1b54