Re: [PATCH 02/13] clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flags

[Konrad Dybcio <konrad.dybcio@linaro.org>]

On 31.05.2024 11:02 AM, Taniya Das wrote:
> Update the GDSC wait_val fields as per the default hardware values as
> otherwise they would lead to GDSC FSM state to be stuck and causing
> failures to power on/off. Also add the GDSC flags as applicable and
> add support to control PCIE GDSC's using collapse vote registers.
> 
> Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  drivers/clk/qcom/gcc-sa8775p.c | 40 ++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c
> index 7bb7aa3a7be5..71fa95f59a0a 100644
> --- a/drivers/clk/qcom/gcc-sa8775p.c
> +++ b/drivers/clk/qcom/gcc-sa8775p.c
> @@ -4203,74 +4203,114 @@ static struct clk_branch gcc_video_axi1_clk = {
>  
>  static struct gdsc pcie_0_gdsc = {
>  	.gdscr = 0xa9004,
> +	.collapse_ctrl = 0x4b104,
> +	.collapse_mask = BIT(0),
> +	.en_rest_wait_val = 0x2,
> +	.en_few_wait_val = 0x2,
> +	.clk_dis_wait_val = 0xf,
>  	.pd = {
>  		.name = "pcie_0_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR,

I have some old dt for this platform, and it doesn't mention the downstream
counterpart flag for it (qcom,support-cfg-gdscr), so please double-check
whether you really want to poll gdcsr + 0x4.

The magic values I trust you have better sources for, the collapse off/masks
look good.

Konrad