[PATCH v5 0/4] Fix Versa3 clock mapping

Biju Das
2023-08-24T10:48:59Z

According to Table 3. ("Output Source") in the 5P35023 datasheet,
the output clock mapping should be 0=REF, 1=SE1, 2=SE2, 3=SE3,
4=DIFF1, 5=DIFF2. But the code uses inverse.

This patch series aims to document clock-output-names in bindings and
fix the mapping in driver.

Also added a fix for 64 by 64 division.

v4->v5:
* Added description for #clock-cells property for clock mapping.
* Updated commit header and description to reflect this change.
* Dropped fixes tag.
* Retained Ack tag from Conor and Krzysztof as it is trivial change.
v3->v4:
* Dropped clock-output-names as there is no validation for it and people
can get it wrong.
* Updated commit header, description and example to reflect this change
* Retained Ack tag from Conor and Krzysztof as it is trivial change.
* Used clamped value for rate calculation in vc3_pll_round_rate().
v2->v3:
* Dropped dts patch and added fix for 64 byte division to this patch
series.
* Added Rb tag from Geert for patch#3
* Added a patch to make vc3_clk_mux enum values depend on vc3_clk enum
values.
v1->v2:
* Updated binding commit description to make it clear it fixes
"assigned-clock-rates" in the example based on 5P35023 datasheet.

Biju Das (4):
dt-bindings: clock: versaclock3: Add description for #clock-cells
property
clk: vc3: Fix 64 by 64 division
clk: vc3: Fix output clock mapping
clk: vc3: Make vc3_clk_mux enum values based on vc3_clk enum values

.../bindings/clock/renesas,5p35023.yaml | 11 ++-
drivers/clk/clk-versaclock3.c | 81 +++++++++----------
2 files changed, 47 insertions(+), 45 deletions(-)

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2.25.1