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Mon, 14 Oct 2024 07:51:06 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49E7p5Zq020221 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 14 Oct 2024 07:51:05 GMT Received: from [10.239.29.179] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 14 Oct 2024 00:51:00 -0700 Message-ID: <96816abb-4e0d-4c60-8ae6-b5a5cd796e99@quicinc.com> Date: Mon, 14 Oct 2024 15:50:53 +0800 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 3/8] dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt To: Krzysztof Kozlowski , Manivannan Sadhasivam CC: , , , , , , , , , , , , , , , , , , , , , References: <20241011104142.1181773-1-quic_qianyu@quicinc.com> <20241011104142.1181773-4-quic_qianyu@quicinc.com> <4802B12B-BAC1-4E99-BDFE-A2340F4A8F24@linaro.org> <3d1d0822-da66-44c8-a328-69804210123c@kernel.org> <65B34B14-76C3-491D-8A58-6D0887889018@linaro.org> Content-Language: en-US From: Qiang Yu In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: c8DC4QGZl6mybIcNqaHlS2FPJub-re1X X-Proofpoint-GUID: c8DC4QGZl6mybIcNqaHlS2FPJub-re1X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=909 lowpriorityscore=0 spamscore=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 phishscore=0 malwarescore=0 impostorscore=0 mlxscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410140056 On 10/12/2024 12:06 AM, Krzysztof Kozlowski wrote: > On 11/10/2024 17:51, Manivannan Sadhasivam wrote: >> >> On October 11, 2024 9:14:31 PM GMT+05:30, Krzysztof Kozlowski wrote: >>> On 11/10/2024 17:42, Manivannan Sadhasivam wrote: >>>> >>>> On October 11, 2024 8:03:58 PM GMT+05:30, Krzysztof Kozlowski wrote: >>>>> On Fri, Oct 11, 2024 at 03:41:37AM -0700, Qiang Yu wrote: >>>>>> Document 'global' SPI interrupt along with the existing MSI interrupts so >>>>>> that QCOM PCIe RC driver can make use of it to get events such as PCIe >>>>>> link specific events, safety events, etc. >>>>> Describe the hardware, not what the driver will do. >>>>> >>>>>> Though adding a new interrupt will break the ABI, it is required to >>>>>> accurately describe the hardware. >>>>> That's poor reason. Hardware was described and missing optional piece >>>>> (because according to your description above everything was working >>>>> fine) is not needed to break ABI. >>>>> >>>> Hardware was described but not completely. 'global' IRQ let's the controller driver to handle PCIe link specific events like Link up, Link down etc... They improve user experience like the driver can use those interrupts to start bus enumeration on its own. So breaking the ABI for good in this case. >>>> >>>>> Sorry, if your driver changes the ABI for this poor reason. >>>>> >>>> Is the above reasoning sufficient? >>> I tried to look for corresponding driver change, but could not, so maybe >>> there is no ABI break in the first place. >> Here it is: >> >> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4581403f67929d02c197cb187c4e1e811c9e762a >> >> Above explanation is good, but >>> still feels like improvement and device could work without global clock. > So there is no ABI break in the first place... Commit is misleading. OK, will remove the description about ABI break in commit message. But may I know in which case ABI will be broken by adding an interrupt in bingdings and what ABI will be broken? > >> It is certainly an improvement but provides a nice user experience as the devices will be enumerated when they get plugged into the slot (like hotplug). Otherwise, users have to rescan the bus every time they plug a device. Also when the device gets removed, driver could retrain the link if link went to a bad state. Otherwise, link will remain in the broken state requiring users to unload/load the driver again. > OK Thanks Mani for your detailed explaination. Can I reword commit message like this: Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPU. This interrupt can be used by the device driver to handle PCIe link specific events such as Link up and Link down, which give the driver a chance to start bus enumeration on its own when link is up and initiate link training if link went to a bad state. This provides a nice user experience. Hence, document it in the binding along with the existing MSI interrupts. Thanks, Qiang > > Best regards, > Krzysztof >