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([2606:29c0:1000:2088:8b84:ea3:7f3d:8a76]) by smtp.gmail.com with ESMTPSA id jz5-20020a0562140e6500b006961cdc3f7csm4386261qvb.85.2024.03.20.19.50.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Mar 2024 19:50:49 -0700 (PDT) Message-ID: <97f8b9e7-983c-435e-8fad-11e71be158b8@gmail.com> Date: Wed, 20 Mar 2024 22:50:48 -0400 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 7/7] clk: rockchip: implement proper GATE_LINK support Content-Language: en-US To: Sebastian Reichel Cc: Ilya K , "andy.yan@rock-chips.com" , "heiko@sntech.de" , "huangtao@rock-chips.com" , "kernel@collabora.com" , "kever.yang@rock-chips.com" , "linux-clk@vger.kernel.org" , "linux-rockchip@lists.infradead.org" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "zhangqing@rock-chips.com" References: <1456131709882456@mail.yandex.ru> <7f4b3f38-50ee-480f-a341-ab577e19bb32@gmail.com> <2rsu6qa3pwbqic6b7ej6txa34jw4ztrnybzcfcfysue2mky37h@dyrdefbimzdn> From: Chad LeClair In-Reply-To: <2rsu6qa3pwbqic6b7ej6txa34jw4ztrnybzcfcfysue2mky37h@dyrdefbimzdn> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Sebastian, On 3/20/24 12:36, Sebastian Reichel wrote: > I also worked on a cleaner solution for the issue you described and > integrated it in the patch adding proper gate clock support. So > please also test with HCLK_NVM not being marked as CRITICAL. > > [0] https://gitlab.collabora.com/hardware-enablement/rockchip-3588/linux/-/commits/rk3588-test > > If everything is fine I will prepare a v9. > >> Hope this additional data point helps! > > Thanks for the detailed analysis. > > Greetings, > > -- Sebastian No luck unfortunately. I still see the SFC dma timeouts. It looks like aclk_nvm_root is still getting disabled. It now has both an enable count of 0 and a prepare count of 0. Unlike your previous version, I _do_ see the driver bound to the device and the rpm_resume() call finds its way to pm_clk_resume(). So it looks like you resolved the original issue I was seeing. However, when I reach __pm_clk_enable() it looks like the clock entry (ce) is not in a good state: (gdb) print *ce $3 = {node = {next = 0xffff0001f0ce1930, prev = 0xffff0001f0ce1930}, con_id = 0xffff0001f0a214f0 "aclk_nvm_root", clk = 0xfffffffffffffffe, status = PCE_STATUS_ERROR, enabled_when_prepared = false} The immediate problem at hand is that ce->status is PCE_STATUS_ERROR so the switch statement will take the default case and return without doing anything. Also the ce->clk pointer looks like some sort of error pointer value so I'm wondering if something went wrong in the setup you were doing in clk_gate_link_probe(). Note: I ran to that same __pm_clk_enable() breakpoint for a number of of GATE_LINK clocks. They all looked to be in that same bad state. I put the "aclk_nvm_root" one in the message here since that is the one that is most relevant to the discussion, but they all look to be broken in the same way. Hopefully this gives you a hint as to what is going on. BTW, In case it is of interest to you or Ilya, I have my "working" tree available here: https://github.com/sesca128/linux-rk3588/tree/v6.8-rk3588-test My quick and dirty hack is at the tip of the branch. The rest is pretty much your rk3588-test branch from a few days ago. -- Chad LeClair