Linux clock framework development
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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Christian Marangi <ansuelsmth@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Ilia Lin <ilia.lin@kernel.org>, Viresh Kumar <vireshk@kernel.org>,
	Nishanth Menon <nm@ti.com>, Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-pm@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling
Date: Mon, 12 Jun 2023 17:20:02 +0300	[thread overview]
Message-ID: <99a68056-a4c9-d475-9245-e0802ffe4c89@linaro.org> (raw)
In-Reply-To: <6486dcef.050a0220.4c054.4c59@mx.google.com>

On 11/06/2023 19:27, Christian Marangi wrote:
> On Mon, Jun 12, 2023 at 08:39:04AM +0300, Dmitry Baryshkov wrote:
>> Implement CPUFreq support for one of the oldest supported Qualcomm
>> platforms, APQ8064. Each core has independent power and frequency
>> control. Additionally the L2 cache is scaled to follow the CPU
>> frequencies (failure to do so results in strange semi-random crashes).
> 
> Hi, can we talk, maybe in private about this interconnect-cpu thing?

Hi, sure. Feel free to ping me on IRC (lumag) or via email. Or we can 
just continue our discussion here, as it might be interesting to other 
people too.

> I see you follow the original implementation of the msm_bus where in
> practice with the use of the kbps the correct clock and voltage was set.
> (and this was also used to set the fabric clock from nominal to fast)
> 
> On ipq806x and I assume other SoC there isn't always a 1:1 map of CPU
> freq and L2 freq. For example on ipq8064 we have max CPU freq of 1.4GHz
> and L2 freq of 1.2GHz, on ipq8065 we have CPU 1.7GHz and L2 of 1.4GHz.

This is also the case for apq8064. The vendor kernel defines 15 
frequencies for L2 cache clock, but then for some reasons all PVS tables 
use just 3 entries from these 15.

> (and even that is curious since I used the debug regs and the cxo
> crystal to measure the clock by hardware (yes i ported the very ancient
> clk-debug to modern kernel and it works and discovered all sort of
> things) the L2 (I assume due to climitation of the hfpll) actually can't
> never reach that frequency (1.4GHz in reality results to something like
> 1.2GHz from what I notice a stable clock is there only with frequency of
> max 1GHz))

I would like to point you to https://github.com/andersson/debugcc/, 
which is a userspace reimplementation of clk-debug. We'd appreciate your 
patches there.

> So my idea was to introduce a simple devfreq driver and use the PASSIVE
> governor where it was added the possibility to link to a CPU frequency
> and with interpolation select the L2 frequency (and voltage)

I stumbled upon this idea, when I was working on the msm8996 and it's 
CBF clock (CBF = interconnect between two core clusters). While it 
should be possible to use DEVFREQ in simple cases (e.g. L2 clock >= 
max(CPU clock), if possible). However real configurations are slightly 
harder.
E.g. for the purpose of this patchset, the relationship for apq8064 is 
the following (in MHz):

  CPU    L2
  384    384
  486    648
  594    648
  702    648
....    ...
1026    648
1134   1134
....   ....
1512   1134
....   ....

It should be noted that msm8960 also used just three values for the L2 
cache frequencies. From what I can see, only msm8x60 made L2 freq 
tightly follow the CPU frequency.

>  From some old comments in ancient qsdk code it was pointed out that due
> to a hw limitation the secondary cpu can't stay at a high clock if L2
> was at the idle clock. (no idea if this is specific to IPQ806x) So this
> might be a cause of your crash? (I also have random crash with L2
> scaling and we are planning to just force the L2 at max frequency)

It might be related. It was more or less the same story with msm8996, 
which was either 'maxcpus=2' or scaling the CBF clock.

> But sorry for all of this (maybe) useless info. I checked the other
> patch and I didn't understand how the different L2 frequency are
> declared and even the voltage. Is this something that will come later?
> I'm very interested in this implementation.

The L2 frequency (<&kraitcc 4>) is converted into bandwidth vote, which 
then goes into the OPP tables. But please also see the discussion 
started at the patch 15.

> 
>>
>> Core voltage is controlled through the SAW2 devices, one for each core.
>> The L2 has two regulators, vdd-mem and vdd-dig.
>>
>> Depenency: [1] for interconnect-clk implementation
>>
>> https://lore.kernel.org/linux-arm-msm/20230512001334.2983048-3-dmitry.baryshkov@linaro.org/
>>
> 

-- 
With best wishes
Dmitry


  reply	other threads:[~2023-06-12 14:22 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-12  5:39 [PATCH 00/18] ARM: qcom: apq8064: support CPU frequency scaling Dmitry Baryshkov
2023-06-11 16:27 ` Christian Marangi
2023-06-12 14:20   ` Dmitry Baryshkov [this message]
2023-06-13 16:19     ` Christian Marangi
2023-06-14 20:18       ` Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 01/18] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs Dmitry Baryshkov
2023-06-14 16:01   ` Krzysztof Kozlowski
2023-06-14 20:11     ` Dmitry Baryshkov
2023-06-21  8:51       ` Krzysztof Kozlowski
2023-06-12  5:39 ` [PATCH 02/18] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml Dmitry Baryshkov
2023-06-14 16:03   ` Krzysztof Kozlowski
2023-06-12  5:39 ` [PATCH 03/18] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Dmitry Baryshkov
2023-06-14 16:05   ` Krzysztof Kozlowski
2023-06-14 22:49     ` Dmitry Baryshkov
2023-06-21  8:46       ` Krzysztof Kozlowski
2023-06-12  5:39 ` [PATCH 04/18] dt-bindings: clock: qcom,krait-cc: Krait core clock controller Dmitry Baryshkov
     [not found]   ` <3ce1bd9b0cb23e4e60b093327e705d69.sboyd@kernel.org>
2023-06-12 22:33     ` Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 05/18] clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 06/18] clk: qcom: krait-cc: export L2 clock as an interconnect Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 07/18] soc: qcom: spm: add support for voltage regulator Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 08/18] cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 09/18] cpufreq: qcom-nvmem: Add support for voltage scaling Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 10/18] cpufreq: qcom-nvmem: drop pvs_ver for format a fuses Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 11/18] cpufreq: qcom-nvmem: provide separate configuration data for apq8064 Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 12/18] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 13/18] ARM: dts: qcom: apq8064: declare SAW2 regulators Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 14/18] ARM: dts: qcom: apq8064: add simple CPUFreq support Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 15/18] ARM: dts: qcom: apq8064: provide voltage scaling tables Dmitry Baryshkov
2023-06-12  9:01   ` Stephan Gerhold
2023-06-12 13:33     ` Dmitry Baryshkov
2023-06-11 22:16       ` Christian Marangi
2023-06-12 13:59       ` Stephan Gerhold
2023-06-12 15:38         ` Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 16/18] ARM: dts: qcom: apq8064: enable passive CPU cooling Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 17/18] ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators Dmitry Baryshkov
2023-06-12  5:39 ` [PATCH 18/18] ARM: dts: qcom: apq8064-ifc6410: " Dmitry Baryshkov

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