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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id w17-20020a2e9bd1000000b002d8e42c1b5fsm1732618ljj.42.2024.04.23.06.14.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Apr 2024 06:14:22 -0700 (PDT) Message-ID: <9adac76c-a1cd-459c-a5e5-5f3daad6a6ff@linaro.org> Date: Tue, 23 Apr 2024 15:14:19 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/8] clk: qcom: gcc-sc7280: Update force mem core bit for UFS ICE clock To: Taniya Das , Stephen Boyd , Michael Turquette , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20240318053555.20405-1-quic_tdas@quicinc.com> <20240318053555.20405-6-quic_tdas@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20240318053555.20405-6-quic_tdas@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 3/18/24 06:35, Taniya Das wrote: > Update the force mem core bit for UFS ICE clock to force the core on signal > to remain active during halt state of the clk. > > Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") You describe the solution, but not the problem. Please state why it's necessary to do so. Konrad