Linux clock framework development
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From: Stephen Boyd <sboyd@kernel.org>
To: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>,
	agross@kernel.org, andersson@kernel.org,
	devicetree@vger.kernel.org, jassisinghbrar@gmail.com,
	konrad.dybcio@linaro.org, krzysztof.kozlowski+dt@linaro.org,
	linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org, mturquette@baylibre.com,
	robh+dt@kernel.org
Cc: quic_varada@quicinc.com, quic_srichara@quicinc.com,
	quic_gokulsri@quicinc.com
Subject: Re: [PATCH 2/3] clk: qcom: apss-ipq-pll: add support for IPQ5018
Date: Tue, 29 Aug 2023 15:34:34 -0700	[thread overview]
Message-ID: <9e3fec3f3bf11ec0722f6277593d96ff.sboyd@kernel.org> (raw)
In-Reply-To: <20230829095423.760641-3-quic_gokulsri@quicinc.com>

Quoting Gokul Sriram Palanisamy (2023-08-29 02:54:22)
> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
> index e170331858cc..bbc25d5eb70d 100644
> --- a/drivers/clk/qcom/apss-ipq-pll.c
> +++ b/drivers/clk/qcom/apss-ipq-pll.c
> @@ -24,6 +24,17 @@ static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = {
>                 [PLL_OFF_TEST_CTL] = 0x30,
>                 [PLL_OFF_TEST_CTL_U] = 0x34,
>         },
> +       [CLK_ALPHA_PLL_TYPE_STROMER] = {
> +               [PLL_OFF_L_VAL] = 0x08,
> +               [PLL_OFF_ALPHA_VAL] = 0x10,
> +               [PLL_OFF_ALPHA_VAL_U] = 0x14,
> +               [PLL_OFF_USER_CTL] = 0x18,
> +               [PLL_OFF_USER_CTL_U] = 0x1c,
> +               [PLL_OFF_CONFIG_CTL] = 0x20,
> +               [PLL_OFF_STATUS] = 0x28,
> +               [PLL_OFF_TEST_CTL] = 0x30,
> +               [PLL_OFF_TEST_CTL_U] = 0x34,
> +       },

Is anything different from STROMER_PLUS?

>         [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
>                 [PLL_OFF_L_VAL] = 0x08,
>                 [PLL_OFF_ALPHA_VAL] = 0x10,
> @@ -73,6 +84,38 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {
>         },
>  };
>  
> +static struct clk_alpha_pll ipq_pll_stromer = {
> +       .offset = 0x0,
> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER],
> +       .flags = SUPPORTS_DYNAMIC_UPDATE,
> +       .clkr = {
> +               .enable_reg = 0x0,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(struct clk_init_data){

const?

> +                       .name = "a53pll",
> +                       .parent_data = &(const struct clk_parent_data) {
> +                               .fw_name = "xo",
> +                       },
> +                       .num_parents = 1,
> +                       .ops = &clk_alpha_pll_stromer_ops,
> +               },
> +       },
> +};
> +
> +static const struct alpha_pll_config ipq5018_pll_config = {
> +       .l = 0x32,
> +       .config_ctl_val = 0x4001075b,
> +       .config_ctl_hi_val = 0x304,
> +       .main_output_mask = BIT(0),
> +       .aux_output_mask = BIT(1),
> +       .early_output_mask = BIT(3),
> +       .alpha_en_mask = BIT(24),
> +       .status_val = 0x3,
> +       .status_mask = GENMASK(10, 8),
> +       .lock_det = BIT(2),
> +       .test_ctl_hi_val = 0x00400003,
> +};
> +
>  static const struct alpha_pll_config ipq5332_pll_config = {
>         .l = 0x3e,
>         .config_ctl_val = 0x4001075b,
> @@ -129,6 +172,12 @@ struct apss_pll_data {
>         const struct alpha_pll_config *pll_config;
>  };
>  
> +static struct apss_pll_data ipq5018_pll_data = {

const?

> +       .pll_type = CLK_ALPHA_PLL_TYPE_STROMER,
> +       .pll = &ipq_pll_stromer,
> +       .pll_config = &ipq5018_pll_config,
> +};
> +
>  static struct apss_pll_data ipq5332_pll_data = {
>         .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
>         .pll = &ipq_pll_stromer_plus,
> @@ -183,7 +232,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
>  
>         if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)
>                 clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
> -       else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
> +       else

Just add both STROMER and STROMER_PLUS. Or make STROMER the same as
STROMER_PLUS locally in this file?

>                 clk_stromer_pll_configure(data->pll, regmap, data->pll_config);
>  
>         ret = devm_clk_register_regmap(dev, &data->pll->clkr);

  reply	other threads:[~2023-08-29 22:35 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-29  9:54 [PATCH 0/3] Add APSS clock driver support for IPQ5018 Gokul Sriram Palanisamy
2023-08-29  9:54 ` [PATCH 1/3] dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible Gokul Sriram Palanisamy
2023-08-29 10:09   ` Krzysztof Kozlowski
2023-08-30  6:40     ` Gokul Sriram P
2023-08-30 19:47       ` Dmitry Baryshkov
2023-08-31  3:26         ` Gokul Sriram P
2023-08-29  9:54 ` [PATCH 2/3] clk: qcom: apss-ipq-pll: add support for IPQ5018 Gokul Sriram Palanisamy
2023-08-29 22:34   ` Stephen Boyd [this message]
2023-08-30  6:37     ` Gokul Sriram P
2023-08-29  9:54 ` [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support Gokul Sriram Palanisamy
2023-08-29 10:12   ` Krzysztof Kozlowski
2023-08-29 10:56     ` Robert Marko
2023-08-29 11:00       ` Dmitry Baryshkov
2023-08-29 11:10       ` Krzysztof Kozlowski
2023-08-29 11:18         ` Robert Marko
2023-08-30  6:48           ` Gokul Sriram P
2023-08-30 19:42             ` Dmitry Baryshkov
2023-08-31  6:10               ` Gokul Sriram P
2023-08-30  6:50       ` Gokul Sriram P

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