Re: [PATCH 08/16] PCI: rzg3s-host: Make inbound window setup SoC-specific

[Claudiu Beznea <claudiu.beznea@tuxon.dev>]

Hi, John,

On 1/14/26 17:33, John Madieu wrote:
> Different RZ/G3 SoCs have different requirements for inbound window
> configuration. While both require power-of-2 sized windows (4KB * 2^N),
> they differ in how non-power-of-2 memory regions are handled:

AFAICT, both RZ/G3S and RZ/G3E HW manuals document the setup of the inbound 
windows the same. Please point me to the proper chapter in case I'm wrong.

Moreover, I tested the code from rzg3e_pcie_set_inbound_windows() (proposed in 
patch 12/16) to setup the inbound window on RZ/G3S and I see no differences in 
terms of mapped regions and functionality. So, unless I'm missing something, I 
think better to use the same code for window setup.

Thank you,
Claudiu

> 
> - RZ/G3S: Uses roundup_pow_of_two() to create a single larger window
>    that may over-map beyond the actual memory region. This approach is
>    simpler but relies on hardware tolerance for over-mapped regions.
> 
> - RZ/G3E: Requires precise coverage without over-mapping. Memory regions
>    must be split into multiple power-of-2 windows, and window sizes must
>    respect address alignment constraints to ensure proper hardware address
>    decoding.
> 
> Move the inbound window sizing and splitting logic to a SoC-specific
> callback to accommodate these differences. This allows each SoC variant
> to implement its own window setup strategy while maintaining the common
> window programming sequence.
> 
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> ---
>   drivers/pci/controller/pcie-rzg3s-host.c | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index fcedccadecf6..a9773e5f25c7 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -223,6 +223,7 @@ struct rzg3s_pcie_host;
>   /**
>    * struct rzg3s_pcie_soc_data - SoC specific data
>    * @init_phy: PHY initialization function
> + * @set_inbound_windows: SoC-specific function to set up inbound windows
>    * @power_resets: array with the resets that need to be de-asserted after
>    *                power-on
>    * @cfg_resets: array with the resets that need to be de-asserted after
> @@ -233,6 +234,9 @@ struct rzg3s_pcie_host;
>    */
>   struct rzg3s_pcie_soc_data {
>   	int (*init_phy)(struct rzg3s_pcie_host *host);
> +	int (*set_inbound_windows)(struct rzg3s_pcie_host *host,
> +				   struct resource_entry *entry,
> +				   int *index);
>   	const char * const *power_resets;
>   	const char * const *cfg_resets;
>   	struct rzg3s_sysc_info sysc_info;
> @@ -1354,7 +1358,7 @@ static int rzg3s_pcie_parse_map_dma_ranges(struct rzg3s_pcie_host *host)
>   	int i = 0, ret;
>   
>   	resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> -		ret = rzg3s_pcie_set_inbound_windows(host, entry, &i);
> +		ret = host->data->set_inbound_windows(host, entry, &i);
>   		if (ret)
>   			return ret;
>   	}
> @@ -1753,6 +1757,7 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_data = {
>   	.cfg_resets = rzg3s_soc_cfg_resets,
>   	.num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets),
>   	.init_phy = rzg3s_soc_pcie_init_phy,
> +	.set_inbound_windows = rzg3s_pcie_set_inbound_windows,
>   	.sysc_info = {
>   		.rst_rsm_b = {
>   			.offset = 0xd74,