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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b79f49b7177sm87268566b.50.2025.12.04.02.16.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Dec 2025 02:17:00 -0800 (PST) Message-ID: <9f8eda70-e077-4925-bc80-f95e35464f87@oss.qualcomm.com> Date: Thu, 4 Dec 2025 11:16:57 +0100 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] clk: qcom: cmnpll: Account for reference clock divider To: Jie Luo , Bjorn Andersson , Michael Turquette , Stephen Boyd , Luo Jie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_pavir@quicinc.com, quic_suruchia@quicinc.com References: <20251128-qcom_ipq5332_cmnpll-v1-0-55127ba85613@oss.qualcomm.com> <20251128-qcom_ipq5332_cmnpll-v1-1-55127ba85613@oss.qualcomm.com> <2d83f0d3-4798-4183-9e3d-9972db706cdb@oss.qualcomm.com> <1d9b953b-5af0-4a81-9182-f1cd47e772f1@oss.qualcomm.com> <5a982965-4964-4f50-87b6-e3b8a1182876@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <5a982965-4964-4f50-87b6-e3b8a1182876@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: bFHhBEz2rq8jrJrd7ISPA0GB4ORHpjXr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA0MDA4MyBTYWx0ZWRfX5M1pA8IJC+Fc 3QrpAiy2ji94c6WxvmGMVVo6U6vFdrpy320GwyhtBxt+hCnWbOJ2HWuLcxBAayOM2C3R6crMrM8 YkzwUO9HnkH0HJVYdsCxTCzfdhAlW/4Y6mhACF6We8HmKvKF6ClscQKS8vfosUhlK4cdfJ4aa7o Nxf8rqnX2Ol2D52UuY8yVbrTxJ47hlOG6juYdrwUwXmkn2g+1+cGmO7u2gCKK4BGk5DtoTE9ib7 f1hcPqTiewsDe6s2dwNV3NQIvme8SNlVcjrT56MneyVca1BWpH2hbR34yUcwadeOZQlkc3Uqn8F hq+SsD4xIGhr0aOxLNo4YEUsA5yI/F7Cptb5guAKj52mYAMdZpRhRvKh0VfITOYWz6bF5HbJlrk 26hrqdA2ypWoyXmiQo06B4wNQKHjRg== X-Proofpoint-ORIG-GUID: bFHhBEz2rq8jrJrd7ISPA0GB4ORHpjXr X-Authority-Analysis: v=2.4 cv=Ctays34D c=1 sm=1 tr=0 ts=69315f9d cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=QLMSgXiTzcT6vDBu34EA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-04_02,2025-12-03_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512040083 On 12/4/25 8:44 AM, Jie Luo wrote: > > > On 12/1/2025 9:42 PM, Konrad Dybcio wrote: >> On 11/28/25 3:29 PM, Jie Luo wrote: >>> >>> >>> On 11/28/2025 7:38 PM, Konrad Dybcio wrote: >>>> On 11/28/25 9:40 AM, Luo Jie wrote: >>>>> The clk_cmn_pll_recalc_rate() function must account for the reference clock >>>>> divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms >>>>> with a reference divider other than 1 calculate incorrect CMN PLL rates. >>>>> For example, on IPQ5332 where the reference divider is 2, the computed rate >>>>> becomes twice the actual output. >>>>> >>>>> Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before >>>>> applying the 2 * FACTOR scaling. This yields the correct rate calculation: >>>>> rate = (parent_rate / ref_div) * 2 * factor. >>>>> >>>>> Maintain backward compatibility with earlier platforms (e.g. IPQ9574, >>>>> IPQ5424, IPQ5018) that use ref_div = 1. >>>> >>>> I'm not sure how to interpret this. Is the value fixed on these platforms >>>> you mentioned, and always shows up as 0? >>>> >>>> Konrad >>> >>> On these platforms the hardware ref_div register comes up with a value >>> of 1 by default. It is, however, still a programmable field and not >>> strictly fixed to 1. >>> >>> The ref_div == 0 check in this patch is only meant as a safety net to >>> avoid a divide‑by‑zero in the rate calculation. >> >> I think some sort of a warning/bugsplat would be good to have here, >> however I see that clk-rcg2.c : clk_gfx3d_determine_rate() apparently >> also silently fixes up a div0.. >> >> Konrad > > I agree it would be better to at least flag this as an invalid > configuration. I can update the code to emit a warning (e.g. WARN_ON > (!ref_div) while still clamping ref_div to a sane value to avoid > crashing in production. That way we preserve the safety net but also > get some visibility if this ever happens. if (WARN_ON(div == 0)) sounds good! Konrad