Linux clock framework development
 help / color / mirror / Atom feed
From: Rohit Agarwal <quic_rohiagar@quicinc.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: <agross@kernel.org>, <bjorn.andersson@linaro.org>,
	<mturquette@baylibre.com>, <sboyd@kernel.org>,
	<robh+dt@kernel.org>, <jassisinghbrar@gmail.com>,
	<linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 4/7] clk: qcom: Add A7 PLL support for SDX65
Date: Mon, 21 Feb 2022 12:57:51 +0530	[thread overview]
Message-ID: <9fb3155e-e23e-fccd-7ab9-88f77de1bb78@quicinc.com> (raw)
In-Reply-To: <20220221054045.GC15108@thinkpad>


On 2/21/2022 11:10 AM, Manivannan Sadhasivam wrote:
> On Mon, Feb 21, 2022 at 10:52:30AM +0530, Rohit Agarwal wrote:
>> Add support for PLL found in Qualcomm SDX65 platforms which is used to
>> provide clock to the Cortex A7 CPU via a mux. This PLL can provide high
>> frequency clock to the CPU above 1GHz as compared to the other sources
>> like GPLL0.
>>
>> In this driver, the power domain is attached to the cpudev. This is
>> required for CPUFreq functionality and there seems to be no better place
>> to do other than this driver (no dedicated CPUFreq driver).
>>
> This tells what the driver is doing but not essentially what this patch does
> i.e., you need to mention how the SDX65 PLL is added to the driver. Since you
> are reusing the existing driver, this needs to be mentioned.
Will update.
>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
>> ---
>>   drivers/clk/qcom/Kconfig  | 6 +++---
>>   drivers/clk/qcom/a7-pll.c | 1 +
>>   2 files changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 42c8741..5159a1d 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -29,11 +29,11 @@ config QCOM_A53PLL
>>   	  devices.
>>   
>>   config QCOM_A7PLL
>> -	tristate "SDX55 A7 PLL"
>> +	tristate "A7 PLL driver for SDX55 and SDX65"
>>   	help
>> -	  Support for the A7 PLL on SDX55 devices. It provides the CPU with
>> +	  Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
>>   	  frequencies above 1GHz.
>> -	  Say Y if you want to support higher CPU frequencies on SDX55
>> +	  Say Y if you want to support higher CPU frequencies on SDX55 and SDX65
>>   	  devices.
>>   
>>   config QCOM_CLK_APCS_MSM8916
>> diff --git a/drivers/clk/qcom/a7-pll.c b/drivers/clk/qcom/a7-pll.c
>> index c4a53e5..adb2121 100644
>> --- a/drivers/clk/qcom/a7-pll.c
>> +++ b/drivers/clk/qcom/a7-pll.c
>> @@ -84,6 +84,7 @@ static int qcom_a7pll_probe(struct platform_device *pdev)
>>   
>>   static const struct of_device_id qcom_a7pll_match_table[] = {
>>   	{ .compatible = "qcom,sdx55-a7pll" },
>> +	{ .compatible = "qcom,sdx65-a7pll" },
> I think here also you can just reuse the "qcom,sdx55-a7pll" compatible.
Ok, Will update. Thanks!
>
> Thanks,
> Mani
>
>>   	{ }
>>   };
>>   MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table);
>> -- 
>> 2.7.4
>>

  reply	other threads:[~2022-02-21  7:28 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-21  5:22 [PATCH v3 0/7] Add APCS support for SDX65 Rohit Agarwal
2022-02-21  5:22 ` [PATCH v3 1/7] dt-bindings: mailbox: Add binding for SDX65 APCS Rohit Agarwal
2022-02-24 20:05   ` Rob Herring
2022-02-21  5:22 ` [PATCH v3 2/7] mailbox: qcom: Add support for SDX65 APCS IPC Rohit Agarwal
2022-02-21  5:35   ` Manivannan Sadhasivam
2022-02-21  7:29     ` Rohit Agarwal
2022-02-21  5:22 ` [PATCH v3 3/7] dt-bindings: clock: Add A7 PLL binding for SDX65 Rohit Agarwal
2022-02-21  5:22 ` [PATCH v3 4/7] clk: qcom: Add A7 PLL support " Rohit Agarwal
2022-02-21  5:40   ` Manivannan Sadhasivam
2022-02-21  7:27     ` Rohit Agarwal [this message]
2022-02-21  5:22 ` [PATCH v3 5/7] ARM: dts: qcom: sdx65: Add support for A7 PLL clock Rohit Agarwal
2022-02-21  5:22 ` [PATCH v3 6/7] ARM: dts: qcom: sdx65: Add support for APCS block Rohit Agarwal
2022-02-21  5:22 ` [PATCH v3 7/7] clk: qcom: Add SDX65 APCS clock controller support Rohit Agarwal
2022-02-21  5:36   ` Manivannan Sadhasivam
2022-02-21  5:44 ` [PATCH v3 0/7] Add APCS support for SDX65 Manivannan Sadhasivam

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=9fb3155e-e23e-fccd-7ab9-88f77de1bb78@quicinc.com \
    --to=quic_rohiagar@quicinc.com \
    --cc=agross@kernel.org \
    --cc=bjorn.andersson@linaro.org \
    --cc=devicetree@vger.kernel.org \
    --cc=jassisinghbrar@gmail.com \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=manivannan.sadhasivam@linaro.org \
    --cc=mturquette@baylibre.com \
    --cc=robh+dt@kernel.org \
    --cc=sboyd@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox