messages from 2020-12-17 18:12:37 to 2020-12-22 19:19:08 UTC [more...]
[PATCH v2 00/48] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs
2020-12-22 19:18 UTC (66+ messages)
` [PATCH v2 01/48] dt-bindings: memory: tegra20: emc: Replace core regulator with power domain
` [PATCH v2 02/48] dt-bindings: memory: tegra30: "
` [PATCH v2 04/48] dt-bindings: host1x: Document OPP and power domain properties
` [PATCH v2 05/48] media: dt: bindings: tegra-vde: "
` [PATCH v2 06/48] dt-bindings: clock: tegra: Document clocks sub-node
` [PATCH v2 07/48] dt-bindings: arm: tegra: Add binding for core power domain
` [PATCH v2 08/48] regulator: Make regulator_sync_voltage() usable by coupled regulators
` [PATCH v2 09/48] opp: Add dev_pm_opp_sync_regulators()
` [PATCH v2 10/48] opp: Add dev_pm_opp_set_voltage()
` [PATCH v2 11/48] opp: Add dev_pm_opp_find_level_ceil()
` [PATCH v2 12/48] opp: Add dev_pm_opp_get_required_pstate()
` [PATCH v2 13/48] opp: Add resource-managed versions of OPP API functions
` [PATCH v2 14/48] opp: Filter out OPPs based on availability of a required-OPP
` [PATCH v2 15/48] opp: Support set_opp() customization without requiring to use regulators
` [PATCH v2 17/48] opp: Correct debug message in _opp_add_static_v2()
` [PATCH v2 19/48] opp: Fix adding OPP entries in a wrong order if rate is unavailable
` [PATCH v2 22/48] soc/tegra: pmc: Fix imbalanced clock disabling in error code path
` [PATCH v2 24/48] soc/tegra: pmc: Ensure that clock rates aren't too high
` [PATCH v2 25/48] soc/tegra: pmc: Print out domain name when reset fails to acquire
` [PATCH v2 28/48] soc/tegra: Introduce core power domain driver
` [PATCH v2 34/48] gpu: host1x: Support power management
` [PATCH v2 41/48] memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table()
` [PATCH v2 43/48] ARM: tegra: Add OPP tables and power domains to Tegra20 device-tree
` [PATCH v2 44/48] ARM: tegra: Add OPP tables and power domains to Tegra30 device-tree
` [PATCH v2 47/48] ARM: tegra: ventana: Support CPU voltage scaling and thermal throttling
` [PATCH v2 48/48] ARM: tegra: cardhu: "
[PATCH 0/2] Add MediaTek MT8192 clock provider device nodes
2020-12-22 13:40 UTC (3+ messages)
` [PATCH 1/2] arm64: dts: mediatek: Add mt8192 clock controllers
` [PATCH 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
[PATCH v6 00/22] Mediatek MT8192 clock support
2020-12-22 13:09 UTC (23+ messages)
` [PATCH v6 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller
` [PATCH v6 02/22] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller
` [PATCH v6 03/22] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller
` [PATCH v6 04/22] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller
` [PATCH v6 05/22] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers
` [PATCH v6 06/22] clk: mediatek: Add dt-bindings of MT8192 clocks
` [PATCH v6 07/22] clk: mediatek: Fix asymmetrical PLL enable and disable control
` [PATCH v6 08/22] clk: mediatek: Add configurable enable control to mtk_pll_data
` [PATCH v6 09/22] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers
` [PATCH v6 10/22] clk: mediatek: Add MT8192 basic clocks support
` [PATCH v6 11/22] clk: mediatek: Add MT8192 audio clock support
` [PATCH v6 12/22] clk: mediatek: Add MT8192 camsys "
` [PATCH v6 13/22] clk: mediatek: Add MT8192 imgsys "
` [PATCH v6 14/22] clk: mediatek: Add MT8192 imp i2c wrapper "
` [PATCH v6 15/22] clk: mediatek: Add MT8192 ipesys "
` [PATCH v6 16/22] clk: mediatek: Add MT8192 mdpsys "
` [PATCH v6 17/22] clk: mediatek: Add MT8192 mfgcfg "
` [PATCH v6 18/22] clk: mediatek: Add MT8192 mmsys "
` [PATCH v6 19/22] clk: mediatek: Add MT8192 msdc "
` [PATCH v6 20/22] clk: mediatek: Add MT8192 scp adsp "
` [PATCH v6 21/22] clk: mediatek: Add MT8192 vdecsys "
` [PATCH v6 22/22] clk: mediatek: Add MT8192 vencsys "
[PATCH v2] clk: mediatek: Remove MT8192 unused clock
2020-12-22 10:50 UTC (3+ messages)
[PATCH 0/5] v3u: add support for RWDT
2020-12-22 9:03 UTC (3+ messages)
` [PATCH 2/5] clk: renesas: r8a779a0: Add RWDT clocks
[PATCH] clk: mediatek: Remove unused MT8192 mcupm clock
2020-12-22 5:35 UTC
[PATCH v2 0/1] Fix kernel panic issues caused by AST2500 Video Engine
2020-12-21 22:32 UTC (2+ messages)
` [PATCH v2 1/1] media: aspeed: fix clock handling logic
[PATCH 0/2] Fix kernel panic issues caused by AST2500 Video Engine
2020-12-21 20:31 UTC (8+ messages)
` [PATCH 2/2] media: aspeed: fix clock handling logic
[PATCH v1 0/2] Add Global Clock controller (GCC) driver for SC7280
2020-12-21 19:00 UTC (3+ messages)
` [PATCH v1 1/2] dt-bindings: clock: Add SC7280 GCC clock binding
[PATCH v7 0/4] Enable Hi3559A SOC clock and HiSilicon Hiedma Controller
2020-12-21 18:55 UTC (5+ messages)
` [PATCH v7 1/4] dt-bindings: Document the hi3559a clock bindings
` [PATCH v7 3/4] dt: bindings: dma: Add DT bindings for HiSilicon Hiedma Controller
[PATCH 01/18] ARM: dts: exynos: correct fuel gauge interrupt trigger level on GT-I9100
2020-12-21 18:47 UTC (7+ messages)
` [RFC 13/18] mfd: max77686: Do not enforce (incorrect) interrupt trigger type
` [RFC 15/18] mfd: max77693: "
` [RFC 17/18] mfd: max14577: "
[GIT PULL] clk changes for the merge window
2020-12-21 18:46 UTC (3+ messages)
[PATCH 0/2] clk: meson8b: cleanup unused code
2020-12-21 18:36 UTC (3+ messages)
` [PATCH 1/2] clk: meson: meson8b: remove compatibility code for old .dtbs
` [PATCH 2/2] dt-bindings: clock: meson8b: remove non-existing clock macros
[PATCH v1] clk: qcom: gcc-sc7180: Mark the camera abh clock always ON
2020-12-21 18:03 UTC
[PATCH] dt-bindings: clk: versaclock5: Miscellaneous fixes and improvements:
2020-12-21 17:21 UTC (6+ messages)
[PATCH v4 0/5] Add new clocks and fix bugs for Ingenic SoCs
2020-12-21 15:52 UTC (6+ messages)
` [PATCH v4 1/5] clk: JZ4780: Add function for disable the second core
` [PATCH v4 2/5] dt-bindings: clock: Add missing clocks for Ingenic SoCs
` [PATCH v4 3/5] clk: Ingenic: Fix problem of MAC clock in Ingenic X1000 and X1830
` [PATCH v4 4/5] clk: Ingenic: Add missing clocks for Ingenic SoCs
` [PATCH v4 5/5] clk: Ingenic: Clean up and reformat the code
[PATCH 1/1] Documentation: media: Document clock handling in camera sensor drivers
2020-12-21 15:25 UTC
[PATCH v2 00/15] soc: xilinx: vcu: Convert driver to clock provider
2020-12-21 15:06 UTC (16+ messages)
` [PATCH v2 01/15] ARM: dts: vcu: define indexes for output clocks
` [PATCH v2 02/15] clk: divider: fix initialization with parent_hw
` [PATCH v2 03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu
` [PATCH v2 04/15] soc: xilinx: vcu: add helper to wait for PLL locked
` [PATCH v2 05/15] soc: xilinx: vcu: add helpers for configuring PLL
` [PATCH v2 06/15] soc: xilinx: vcu: implement PLL disable
` [PATCH v2 07/15] soc: xilinx: vcu: register PLL as fixed rate clock
` [PATCH v2 08/15] soc: xilinx: vcu: implement clock provider for output clocks
` [PATCH v2 09/15] soc: xilinx: vcu: make pll post divider explicit
` [PATCH v2 10/15] soc: xilinx: vcu: make the PLL configurable
` [PATCH v2 11/15] soc: xilinx: vcu: remove calculation of PLL configuration
` [PATCH v2 12/15] soc: xilinx: vcu: use bitfields for register definition
` [PATCH v2 13/15] soc: xilinx: vcu: fix repeated word the in comment
` [PATCH v2 14/15] soc: xilinx: vcu: fix alignment to open parenthesis
` [PATCH v2 15/15] clk: xilinx: move xlnx_vcu clock driver from soc
[PATCH 1/2] clk: axi-clkgen: add support for ZynqMP (UltraScale)
2020-12-21 14:42 UTC (2+ messages)
` [PATCH 2/2] dt-bindings: clock: adi,axi-clkgen: add Zynq & ZynqMP compatible strings
About rounding in the clk framework [Was: Re: [PATCH 4/7] pwm: jz4740: Improve algorithm of clock calculation]
2020-12-21 13:57 UTC (3+ messages)
clk_get_rate for disabled clks
2020-12-21 12:57 UTC (2+ messages)
[PATCH 00/12] soc: xilinx: vcu: Convert driver to clock provider
2020-12-21 9:19 UTC (10+ messages)
` [PATCH 08/12] soc: xilinx: vcu: implement clock provider for output clocks
[PATCH 0/2] clk: provide new devm helpers for prepared and enabled clocks
2020-12-21 9:29 UTC (4+ messages)
` [PATCH 1/2] "
[PATCH 0/6] ARM: mstar: Basic MPLL support
2020-12-21 8:51 UTC (11+ messages)
` [PATCH 2/6] dt-bindings: clk: mstar msc313 mpll binding description
` [PATCH 3/6] clk: mstar: MStar/SigmaStar MPLL driver
[PATCH] clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
2020-12-21 1:47 UTC (4+ messages)
[PATCH 0/2] RISC-V K210 SoC clock driver documentation
2020-12-20 18:45 UTC (5+ messages)
` [PATCH 1/2] dt-bindings: Add Canaan vendor prefix
` [PATCH 2/2] dt-binding: clock: Document canaan,k210-clk bindings
[PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621
2020-12-20 9:37 UTC (7+ messages)
` [PATCH v5 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks
` [PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation
` [PATCH v5 3/6] clk: ralink: add clock driver for mt7621 SoC
` [PATCH v5 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'
` [PATCH v5 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'
` [PATCH v5 6/6] MAINTAINERS: add MT7621 CLOCK maintainer
[PATCH v10 00/23] RISC-V Kendryte K210 support improvements
2020-12-20 8:58 UTC (12+ messages)
` [PATCH v10 09/23] dt-binding: clock: Document canaan,k210-clk bindings
[PATCH v3] drivers: clk: make gpio-gated clock support optional
2020-12-20 5:30 UTC (3+ messages)
[PATCH 0/2] Enable usage of Marvell FW SIP services
2020-12-20 0:16 UTC (3+ messages)
` [PATCH 2/2] clk: mvebu: use firmware SiP service for accessing dfx register set
[PATCH] clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"
2020-12-20 0:09 UTC (4+ messages)
[PATCH] clk: ingenic: Fix divider calculation with div tables
2020-12-20 0:05 UTC (2+ messages)
[PATCH] clk: sunxi-ng: Make sure divider tables have sentinel
2020-12-19 23:54 UTC (2+ messages)
[PATCH] clk: s2mps11: Fix a resource leak in error handling paths in the probe function
2020-12-19 23:53 UTC (2+ messages)
[PATCH resend] clk: si5351: Wait for bit clear after PLL reset
2020-12-19 23:50 UTC (2+ messages)
[PATCH] clk: at91: sam9x60: remove atmel,osc-bypass support
2020-12-19 23:32 UTC (2+ messages)
[PATCH v6 00/11] clk: at91: clk-master: re-factor master clock
2020-12-19 23:32 UTC (25+ messages)
` [PATCH v6 01/11] clk: at91: sama7g5: fix compilation error
` [PATCH v6 02/11] dt-bindings: clock: at91: add sama7g5 pll defines
` [PATCH v6 03/11] clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
` [PATCH v6 04/11] clk: at91: clk-master: add 5th divisor for mck master
` [PATCH v6 05/11] clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
` [PATCH v6 06/11] clk: at91: clk-sam9x60-pll: allow runtime changes for pll
` [PATCH v6 07/11] clk: at91: sama7g5: remove mck0 from parent list of other clocks
` [PATCH v6 08/11] clk: at91: sama7g5: decrease lower limit for MCK0 rate
` [PATCH v6 09/11] clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
` [PATCH v6 10/11] clk: at91: clk-master: re-factor master clock
` [PATCH v6 11/11] clk: at91: sama7g5: register cpu clock
[PATCH] clk: bcm: dvp: Add MODULE_DEVICE_TABLE()
2020-12-19 19:48 UTC (2+ messages)
[PATCH] clk: bcm: dvp: drop a variable that is assigned to only
2020-12-19 19:48 UTC (2+ messages)
[PATCH 0/1] dt-bindings: clock: imx8qxp-lpcg: eliminate yamllint warnings
2020-12-19 19:44 UTC (6+ messages)
` [PATCH 1/1] "
[PATCH 0/3] clk: renesas: r8a779a0: Add FCP and VSP support
2020-12-18 13:30 UTC (7+ messages)
` [PATCH 1/3] clk: renesas: r8a779a0: Add FCPVD clock support
` [PATCH 2/3] clk: renesas: r8a779a0: Add VSPD "
` [PATCH 3/3] clk: renesas: r8a779a0: Add VSPX "
[PATCH 1/2] thermal: armada: ap806: use firmware SiP services for thermal operations
2020-12-18 7:12 UTC (3+ messages)
[PATCH] clk: exynos7: Mark aclk_fsys1_200 as critical
2020-12-17 21:08 UTC (3+ messages)
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