messages from 2025-10-22 13:51:46 to 2025-10-27 09:51:02 UTC [more...]
[PATCH v2 0/8] Add support for i.MX8ULP's SIM LPAV
2025-10-27 9:50 UTC (10+ messages)
` [PATCH v2 1/8] reset: imx8mp-audiomix: Fix bad mask values
` [PATCH v2 2/8] dt-bindings: clock: document 8ULP's SIM LPAV
` [PATCH v2 3/8] clk: imx: add driver for imx8ulp's sim lpav
[PATCH v5 0/7] clk: rockchip: Add clock controller for the
2025-10-27 8:41 UTC (8+ messages)
` [PATCH v5 1/7] clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll()
` [PATCH v5 2/7] dt-bindings: clock, reset: Add support for rv1126b
` [PATCH v5 3/7] clk: rockchip: Add clock controller for the RV1126B
` [PATCH v5 4/7] dt-bindings: clock: Add support for rockchip pvtpll
` [PATCH v5 5/7] clk: rockchip: add support for pvtpll clk
` [PATCH v5 6/7] dt-bindings: clock: rockchip: Add RK3506 clock and reset unit
` [PATCH v5 7/7] clk: rockchip: Add clock and reset driver for RK3506
[PATCH 0/2] clk: improve the execution efficiency of determine_rate()
2025-10-27 8:47 UTC (4+ messages)
` [PATCH 2/2] clk: divider: "
[PATCH v15 0/3] Add support for AST2700 clk driver
2025-10-27 6:24 UTC (3+ messages)
` [PATCH v15 3/3] clk: aspeed: add AST2700 clock driver
[PATCH] clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src
2025-10-27 2:03 UTC (6+ messages)
` "
[PATCH] dt-bindings: Remove extra blank lines
2025-10-27 1:36 UTC (17+ messages)
[PATCH v2 0/6] clk/reset: anlogic: add support for DR1V90 SoC
2025-10-27 1:46 UTC (10+ messages)
` [PATCH v2 1/6] clk: correct clk_div_mask() return value for width == 32
` [PATCH v2 2/6] dt-bindings: clock: add Anlogic DR1V90 CRU
` [PATCH v2 3/6] clk: anlogic: add cru support for Anlogic DR1V90 SoC
` [PATCH v2 4/6] reset: anlogic: add support for Anlogic DR1V90 resets
` [PATCH v2 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90
` [PATCH v2 6/6] MAINTAINERS: Add entry for Anlogic DR1V90 SoC drivers
[PATCH v1] clk: tegra: clk-dfll: scale force_val with coefficient according to whether cg_scale is set
2025-10-26 23:18 UTC
[PATCH AUTOSEL 6.17-6.12] clk: scmi: Add duty cycle ops only when duty cycle is supported
2025-10-26 23:16 UTC (3+ messages)
` [PATCH AUTOSEL 6.17-6.12] clk: scmi: migrate round_rate() to determine_rate()
[PATCH v5 21/23] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI
2025-10-26 22:24 UTC (5+ messages)
` [PATCH v5 22/23] ARM: tegra: add CSI nodes for Tegra20 and Tegra30
` [PATCH v5 23/23] staging: media: tegra-video: add CSI support "
[PATCH v1 0/7] clk: mediatek: Add support for SPMI Clock Controllers
2025-10-26 7:29 UTC (10+ messages)
` [PATCH v1 1/7] clk: mediatek: Split out registration from mtk_clk_register_gates()
` [PATCH v1 2/7] clk: mediatek: clk-gate: Simplify and optimize registration iter
` [PATCH v1 3/7] clk: mediatek: clk-mtk: Split and rename __mtk_clk_simple_probe()
` [PATCH v1 4/7] clk: mediatek: Add and wire up mtk_spmi_clk_register_gates()
` [PATCH v1 5/7] clk: mediatek: Add support to register SPMI Clock Controllers
` [PATCH v1 6/7] dt-bindings: clock: Describe MT6685 PM/Clock IC Clock Controller
` [PATCH v1 7/7] clk: mediatek: Add support for "
[PATCH v2 0/2] reset: remove last remaining user of the legacy lookup and drop unused code
2025-10-26 1:38 UTC (6+ messages)
` [PATCH v2 1/2] clk: davinci: psc: drop unused reset lookup
` [PATCH v2 2/2] reset: remove legacy reset lookup code
phy: marvell: phy-mvebu-cp110-comphy: link failure and lockup built as module (=M)
2025-10-25 14:21 UTC
[PATCH 0/3] clk: renesas: r9a09g056: Add DSI, CRU, ISP clock and reset support
2025-10-25 2:05 UTC (10+ messages)
` [PATCH 1/3] clk: renesas: r9a09g056: Add clocks and resets for DSI and LCDC modules
` [PATCH 2/3] clk: renesas: r9a09g056: Add support for PLLVDO, CRU clocks, and resets
` [PATCH 3/3] clk: renesas: r9a09g056: Add clock and reset entries for ISP
[PATCH v2 0/5] clk: samsung: introduce exynos8890 clock driver
2025-10-24 13:51 UTC (6+ messages)
` [PATCH v2 5/5] "
[PATCH v2] clk: qcom: gcc: Update the SDCC clock to use shared_floor_ops
2025-10-24 13:12 UTC (3+ messages)
[PATCH] clk: do not trust cached rates for disabled clocks
2025-10-24 11:23 UTC (10+ messages)
issue with [PATCH v6 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct
2025-10-24 11:21 UTC (4+ messages)
` Aw: "
[PATCH v5 0/9] Redo PolarFire SoC's mailbox/clock devicestrees and related code
2025-10-24 10:30 UTC (13+ messages)
` [PATCH v5 2/9] soc: microchip: add mfd drivers for two syscon regions on PolarFire SoC
` [PATCH v5 3/9] reset: mpfs: add non-auxiliary bus probing
` [PATCH v5 5/9] clk: microchip: mpfs: use regmap for clocks
[PATCH 00/10] Add TSU support for RZ/T2H and RZ/N2H
2025-10-24 10:16 UTC (13+ messages)
` [PATCH 01/10] clk: renesas: r9a09g077: add TSU module clock
` [PATCH 02/10] thermal: renesas: rzg3e: make reset optional
` [PATCH 03/10] thermal: renesas: rzg3e: make min and max temperature per-chip
` [PATCH 04/10] thermal: renesas: rzg3e: make calibration value retrieval per-chip
` [PATCH 05/10] dt-bindings: thermal: r9a09g047-tsu: document RZ/T2H and RZ/N2H
` [PATCH 06/10] thermal: renesas: rzg3e: add support for "
` [PATCH 07/10] arm64: dts: renesas: r9a09g077: add OPP table
` [PATCH 08/10] arm64: dts: renesas: r9a09g087: "
` [PATCH 09/10] arm64: dts: renesas: r9a09g077: add TSU and thermal zones support
` [PATCH 10/10] arm64: dts: renesas: r9a09g087: "
[PATCH 0/2] Add XSPI core and module clocks to Renesas R9A09G077/87 SoCs
2025-10-24 10:09 UTC (5+ messages)
` [PATCH 1/2] dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs
` [PATCH 2/2] clk: renesas: r9a09g077: Add xSPI core and module clocks
[PATCH v3 0/4] Add the support for SM8750 Video clock controller
2025-10-24 8:39 UTC (7+ messages)
` [PATCH v3 1/4] clk: qcom: branch: Extend invert logic for branch2 mem clocks
` [PATCH v3 2/4] clk: qcom: ecpricc-qdu100: Add mem_enable_mask to the clock memory branch
` [PATCH v3 3/4] dt-bindings: clock: qcom: Add SM8750 video clock controller
` [PATCH v3 4/4] clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750
[PATCH v3 0/2] Remove hard coded values for MIPI-DSI
2025-10-24 7:31 UTC (11+ messages)
` [PATCH v3 1/2] clk: renesas: rzg2l: Remove DSI clock rate restrictions
` [PATCH v3 2/2] drm: renesas: rz-du: Set DSI divider based on target MIPI device
[Resend PATCH v4 0/7] clk: rockchip: Add clock controller for the RV1126B and RK3506
2025-10-24 7:14 UTC (3+ messages)
` [PATCH v4 6/7] dt-bindings: clock: rockchip: Add RK3506 clock and reset unit
[PATCH v2] clk: imx: imx8mp-audiomix: use devm_auxiliary_device_create() to simple code
2025-10-24 2:15 UTC (2+ messages)
[PATCH v5 0/6] clk: Support spread spectrum and use it in clk-scmi
2025-10-23 14:48 UTC (5+ messages)
` [PATCH v5 6/6] clk: scmi: Add i.MX95 OEM extension support for SCMI clock driver
[PATCH v4 0/4] Non-const bitfield helpers
2025-10-23 11:38 UTC (8+ messages)
` [PATCH v4 2/4] bitfield: Add non-constant field_{prep,get}() helpers
[GIT PULL] clk: socfpga: update for v6.19
2025-10-23 11:45 UTC
[PATCH v2] dt-bindings: arm: Convert Marvell CP110 System Controller to DT schema
2025-10-23 11:12 UTC (3+ messages)
[PATCH v11 0/7] Add support for DU/DSI clocks and DSI driver support for the Renesas RZ/V2H(P) SoC
2025-10-23 9:06 UTC (6+ messages)
[PATCH v4 2/7] dt-bindings: clock, reset: Add support for rv1126b
2025-10-23 8:43 UTC (2+ messages)
` [v4 "
[PATCH 0/9] Add support for Clock controllers for Kaanapali
2025-10-23 8:42 UTC (10+ messages)
` [PATCH 4/9] clk: qcom: rpmh: Add support for Kaanapali rpmh clocks
` [PATCH 5/9] clk: qcom: Update TCSR clock driver for Kaanapali
[PATCH v7 0/2] clk: add support for TI CDCE6214
2025-10-23 8:24 UTC (3+ messages)
` [PATCH v7 2/2] clk: add TI CDCE6214 clock driver
[PATCH v7 0/2] Add driver support for ESWIN eic700 SoC clock controller
2025-10-23 7:18 UTC (3+ messages)
` [PATCH v7 1/2] dt-bindings: clock: eswin: Documentation for eic7700 SoC
` [PATCH v7 2/2] clock: eswin: Add eic7700 clock driver
[PATCH] clk: imx: imx8mp-audiomix: Use the auxiliary device creation helper
2025-10-23 6:56 UTC (3+ messages)
[PATCH v2 0/2] Remove hard coded values for MIPI-DSI
2025-10-22 23:56 UTC (4+ messages)
` [PATCH v2 1/2] clk: renesas: rzg2l: Remove DSI clock rate restrictions
[PATCH 00/11] allwinner: a523: Enable I2S and SPDIF TX
2025-10-22 19:07 UTC (2+ messages)
` (subset) "
[PATCH 0/7] Add generic PHY driver used by MACB/GEM on EyeQ5
2025-10-22 17:55 UTC (9+ messages)
` [PATCH 1/7] dt-bindings: soc: mobileye: OLB is an Ethernet PHY provider "
` [PATCH 2/7] phy: Add driver for EyeQ5 Ethernet PHY wrapper
` [PATCH 3/7] clk: eyeq: use the auxiliary device creation helper
` [PATCH 4/7] clk: eyeq: add EyeQ5 children auxiliary device for generic PHYs
` [PATCH 5/7] reset: eyeq: drop device_set_of_node_from_dev() done by parent
` [PATCH 6/7] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers
` [PATCH 7/7] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs
[PATCH v2 0/6] Add RTC support for the Renesas RZ/V2H SoC
2025-10-22 17:42 UTC (3+ messages)
` [PATCH v2 2/6] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support
[PATCH 0/2] Fix Agera PLL config of CAMCC for SM6350 & SM7150
2025-10-22 15:19 UTC (5+ messages)
` [PATCH 1/2] clk: qcom: camcc-sm6350: Fix PLL config of PLL2
[PATCH v5 00/23] tegra-video: add CSI support for Tegra20 and Tegra30
2025-10-22 14:20 UTC (21+ messages)
` [PATCH v5 01/23] clk: tegra: set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114
` [PATCH v5 02/23] dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
` [PATCH v5 03/23] clk: tegra30: add CSI pad clock gates
` [PATCH v5 04/23] dt-bindings: display: tegra: document Tegra30 VI and VIP
` [PATCH v5 05/23] staging: media: tegra-video: expand VI and VIP support to Tegra30
` [PATCH v5 06/23] staging: media: tegra-video: vi: adjust get_selection op check
` [PATCH v5 07/23] staging: media: tegra-video: vi: add flip controls only if no source controls are provided
` [PATCH v5 08/23] staging: media: tegra-video: csi: move CSI helpers to header
` [PATCH v5 09/23] gpu: host1x: convert MIPI to use operation function pointers
` [PATCH v5 10/23] dt-bindings: display: tegra: document Tegra132 MIPI calibration device
` [PATCH v5 11/23] staging: media: tegra-video: vi: improve logic of source requesting
` [PATCH v5 12/23] staging: media: tegra-video: csi: move avdd-dsi-csi-supply from VI to CSI
` [PATCH v5 13/23] arm64: tegra: move avdd-dsi-csi-supply into CSI node
` [PATCH v5 14/23] staging: media: tegra-video: tegra20: set correct maximum width and height
` [PATCH v5 15/23] staging: media: tegra-video: tegra20: add support for second output of VI
` [PATCH v5 16/23] staging: media: tegra-video: tegra20: adjust format align calculations
` [PATCH v5 17/23] staging: media: tegra-video: tegra20: set VI HW revision
` [PATCH v5 18/23] staging: media: tegra-video: tegra20: increase maximum VI clock frequency
` [PATCH v5 19/23] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422/YUV420p 1X16
` [PATCH v5 20/23] staging: media: tegra-video: tegra20: adjust luma buffer stride
[PATCH] dt-bindings: arm: Convert Marvell AP80x System Controller to DT schema
2025-10-22 14:12 UTC (2+ messages)
[PATCH] dt-bindings: arm: Convert Marvell CP110 System Controller to DT schema
2025-10-22 14:11 UTC (2+ messages)
[PATCH v2 0/2] Implement Send and Sync for clk
2025-10-22 14:08 UTC (6+ messages)
` [PATCH v2 1/2] rust: clk: implement Send and Sync
[PATCH 0/3] clk: amlogic: optimize the PLL driver
2025-10-22 14:07 UTC (4+ messages)
` [PATCH 2/3] clk: amlogic: Optimize PLL enable timing
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