* [PATCH 0/2] Add XSPI core and module clocks to Renesas R9A09G077/87 SoCs @ 2025-10-14 15:13 Prabhakar 2025-10-14 15:13 ` [PATCH 1/2] dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs Prabhakar 2025-10-14 15:13 ` [PATCH 2/2] clk: renesas: r9a09g077: Add xSPI core and module clocks Prabhakar 0 siblings, 2 replies; 7+ messages in thread From: Prabhakar @ 2025-10-14 15:13 UTC (permalink / raw) To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm Cc: linux-renesas-soc, linux-clk, linux-kernel, devicetree, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Hi all, This patch set adds support for the core and module clocks used by the xSPI (Expanded SPI) IP on the R9A09G077 and R9A09G087 SoCs. Cheers, Prabhakar Lad Prabhakar (2): dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs clk: renesas: r9a09g077: Add xSPI core and module clocks drivers/clk/renesas/r9a09g077-cpg.c | 35 ++++++++++++++++++- .../clock/renesas,r9a09g077-cpg-mssr.h | 2 ++ .../clock/renesas,r9a09g087-cpg-mssr.h | 2 ++ 3 files changed, 38 insertions(+), 1 deletion(-) -- 2.43.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs 2025-10-14 15:13 [PATCH 0/2] Add XSPI core and module clocks to Renesas R9A09G077/87 SoCs Prabhakar @ 2025-10-14 15:13 ` Prabhakar 2025-10-14 17:48 ` Conor Dooley 2025-10-24 10:09 ` Geert Uytterhoeven 2025-10-14 15:13 ` [PATCH 2/2] clk: renesas: r9a09g077: Add xSPI core and module clocks Prabhakar 1 sibling, 2 replies; 7+ messages in thread From: Prabhakar @ 2025-10-14 15:13 UTC (permalink / raw) To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm Cc: linux-renesas-soc, linux-clk, linux-kernel, devicetree, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Add clock definitions for XSPI0/1 to both R9A09G077 and R9A09G087 SoCs. These definitions are required for describing XSPI devices in DT Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 2 ++ include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index 2a805e06487b..9eaedca6a616 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -31,5 +31,7 @@ #define R9A09G077_ETCLKC 19 #define R9A09G077_ETCLKD 20 #define R9A09G077_ETCLKE 21 +#define R9A09G077_XSPI_CLK0 22 +#define R9A09G077_XSPI_CLK1 23 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h index 09da0ad33be6..606468ac49a4 100644 --- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -31,5 +31,7 @@ #define R9A09G087_ETCLKC 19 #define R9A09G087_ETCLKD 20 #define R9A09G087_ETCLKE 21 +#define R9A09G087_XSPI_CLK0 22 +#define R9A09G087_XSPI_CLK1 23 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs 2025-10-14 15:13 ` [PATCH 1/2] dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs Prabhakar @ 2025-10-14 17:48 ` Conor Dooley 2025-10-24 10:09 ` Geert Uytterhoeven 1 sibling, 0 replies; 7+ messages in thread From: Conor Dooley @ 2025-10-14 17:48 UTC (permalink / raw) To: Prabhakar Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-renesas-soc, linux-clk, linux-kernel, devicetree, Biju Das, Fabrizio Castro, Lad Prabhakar [-- Attachment #1: Type: text/plain, Size: 75 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: not-applicable [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs 2025-10-14 15:13 ` [PATCH 1/2] dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs Prabhakar 2025-10-14 17:48 ` Conor Dooley @ 2025-10-24 10:09 ` Geert Uytterhoeven 1 sibling, 0 replies; 7+ messages in thread From: Geert Uytterhoeven @ 2025-10-24 10:09 UTC (permalink / raw) To: Prabhakar Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-renesas-soc, linux-clk, linux-kernel, devicetree, Biju Das, Fabrizio Castro, Lad Prabhakar On Tue, 14 Oct 2025 at 17:13, Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add clock definitions for XSPI0/1 to both R9A09G077 and R9A09G087 SoCs. > These definitions are required for describing XSPI devices in DT > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in a branch shared by renesas-devel and renesas-clk once the issues around PATCH 2/2 are resolved. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] clk: renesas: r9a09g077: Add xSPI core and module clocks 2025-10-14 15:13 [PATCH 0/2] Add XSPI core and module clocks to Renesas R9A09G077/87 SoCs Prabhakar 2025-10-14 15:13 ` [PATCH 1/2] dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs Prabhakar @ 2025-10-14 15:13 ` Prabhakar 2025-10-24 10:08 ` Geert Uytterhoeven 1 sibling, 1 reply; 7+ messages in thread From: Prabhakar @ 2025-10-14 15:13 UTC (permalink / raw) To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm Cc: linux-renesas-soc, linux-clk, linux-kernel, devicetree, Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Add module and core clocks used by xSPI (Expanded SPI) IP on the R9A09G077 SoC. The xSPI block uses PCLKH as its bus clock, while the operation clock (XSPI_CLKn) is derived from PLL4. To support this, define new selectors and dividers (FSELXSPI0/1 and DIVSEL_XSPI0/1) in SCKCR. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/clk/renesas/r9a09g077-cpg.c | 35 ++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c index 4ec6c4ddc5f5..e08b1a589ccc 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -54,6 +54,10 @@ #define DIVSCI3ASYNC CONF_PACK(SCKCR3, 12, 2) #define DIVSCI4ASYNC CONF_PACK(SCKCR3, 14, 2) +#define FSELXSPI0 CONF_PACK(SCKCR, 0, 3) +#define FSELXSPI1 CONF_PACK(SCKCR, 8, 3) +#define DIVSEL_XSPI0 CONF_PACK(SCKCR, 6, 1) +#define DIVSEL_XSPI1 CONF_PACK(SCKCR, 14, 1) #define SEL_PLL CONF_PACK(SCKCR, 22, 1) @@ -72,7 +76,7 @@ enum rzt2h_clk_types { enum clk_ids { /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK = R9A09G077_ETCLKE, + LAST_DT_CORE_CLK = R9A09G077_XSPI_CLK1, /* External Input Clocks */ CLK_EXTAL, @@ -88,12 +92,16 @@ enum clk_ids { CLK_SEL_CLK_PLL2, CLK_SEL_CLK_PLL4, CLK_PLL4D1, + CLK_PLL4D1_DIV3, + CLK_PLL4D1_DIV4, CLK_SCI0ASYNC, CLK_SCI1ASYNC, CLK_SCI2ASYNC, CLK_SCI3ASYNC, CLK_SCI4ASYNC, CLK_SCI5ASYNC, + CLK_DIVSELXSPI0_SCKCR, + CLK_DIVSELXSPI1_SCKCR, /* Module Clocks */ MOD_CLK_BASE, @@ -105,6 +113,15 @@ static const struct clk_div_table dtable_1_2[] = { {0, 0}, }; +static const struct clk_div_table dtable_6_8_16_32_64[] = { + {6, 64}, + {5, 32}, + {4, 16}, + {3, 8}, + {2, 6}, + {0, 0}, +}; + static const struct clk_div_table dtable_24_25_30_32[] = { {0, 32}, {1, 30}, @@ -119,6 +136,7 @@ static const char * const sel_clk_pll0[] = { ".loco", ".pll0" }; static const char * const sel_clk_pll1[] = { ".loco", ".pll1" }; static const char * const sel_clk_pll2[] = { ".loco", ".pll2" }; static const char * const sel_clk_pll4[] = { ".loco", ".pll4" }; +static const char * const sel_clk_pll4d1_div3_div4[] = { ".pll4d1_div3", ".pll4d1_div4" }; static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { /* External Clock Inputs */ @@ -154,6 +172,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { DEF_DIV(".sci5async", CLK_SCI5ASYNC, CLK_PLL4D1, DIVSCI5ASYNC, dtable_24_25_30_32), + DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1), + DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1), + DEF_MUX(".divselxspi0", CLK_DIVSELXSPI0_SCKCR, DIVSEL_XSPI0, + sel_clk_pll4d1_div3_div4, + ARRAY_SIZE(sel_clk_pll4d1_div3_div4), CLK_MUX_HIWORD_MASK), + DEF_MUX(".divselxspi1", CLK_DIVSELXSPI1_SCKCR, DIVSEL_XSPI1, + sel_clk_pll4d1_div3_div4, + ARRAY_SIZE(sel_clk_pll4d1_div3_div4), CLK_MUX_HIWORD_MASK), + /* Core output clk */ DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0, dtable_1_2), @@ -178,9 +205,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { DEF_FIXED("ETCLKC", R9A09G077_ETCLKC, CLK_SEL_CLK_PLL1, 10, 1), DEF_FIXED("ETCLKD", R9A09G077_ETCLKD, CLK_SEL_CLK_PLL1, 20, 1), DEF_FIXED("ETCLKE", R9A09G077_ETCLKE, CLK_SEL_CLK_PLL1, 40, 1), + DEF_DIV("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR, + FSELXSPI0, dtable_6_8_16_32_64), + DEF_DIV("XSPI_CLK1", R9A09G077_XSPI_CLK1, CLK_DIVSELXSPI1_SCKCR, + FSELXSPI1, dtable_6_8_16_32_64), }; static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = { + DEF_MOD("xspi0", 4, R9A09G077_CLK_PCLKH), + DEF_MOD("xspi1", 5, R9A09G077_CLK_PCLKH), DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC), DEF_MOD("sci1fck", 9, CLK_SCI1ASYNC), DEF_MOD("sci2fck", 10, CLK_SCI2ASYNC), -- 2.43.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] clk: renesas: r9a09g077: Add xSPI core and module clocks 2025-10-14 15:13 ` [PATCH 2/2] clk: renesas: r9a09g077: Add xSPI core and module clocks Prabhakar @ 2025-10-24 10:08 ` Geert Uytterhoeven 2025-10-27 21:04 ` Lad, Prabhakar 0 siblings, 1 reply; 7+ messages in thread From: Geert Uytterhoeven @ 2025-10-24 10:08 UTC (permalink / raw) To: Prabhakar Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-renesas-soc, linux-clk, linux-kernel, devicetree, Biju Das, Fabrizio Castro, Lad Prabhakar Hi Prabhakar, On Tue, 14 Oct 2025 at 17:13, Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add module and core clocks used by xSPI (Expanded SPI) IP on the > R9A09G077 SoC. > > The xSPI block uses PCLKH as its bus clock, while the operation clock > (XSPI_CLKn) is derived from PLL4. To support this, define new selectors > and dividers (FSELXSPI0/1 and DIVSEL_XSPI0/1) in SCKCR. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/drivers/clk/renesas/r9a09g077-cpg.c > +++ b/drivers/clk/renesas/r9a09g077-cpg.c > @@ -105,6 +113,15 @@ static const struct clk_div_table dtable_1_2[] = { > {0, 0}, > }; > > +static const struct clk_div_table dtable_6_8_16_32_64[] = { > + {6, 64}, > + {5, 32}, > + {4, 16}, > + {3, 8}, > + {2, 6}, > + {0, 0}, > +}; > + > static const struct clk_div_table dtable_24_25_30_32[] = { > {0, 32}, > {1, 30}, > @@ -119,6 +136,7 @@ static const char * const sel_clk_pll0[] = { ".loco", ".pll0" }; > static const char * const sel_clk_pll1[] = { ".loco", ".pll1" }; > static const char * const sel_clk_pll2[] = { ".loco", ".pll2" }; > static const char * const sel_clk_pll4[] = { ".loco", ".pll4" }; > +static const char * const sel_clk_pll4d1_div3_div4[] = { ".pll4d1_div3", ".pll4d1_div4" }; > > static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { > /* External Clock Inputs */ > @@ -154,6 +172,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { > DEF_DIV(".sci5async", CLK_SCI5ASYNC, CLK_PLL4D1, DIVSCI5ASYNC, > dtable_24_25_30_32), > > + DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1), > + DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1), > + DEF_MUX(".divselxspi0", CLK_DIVSELXSPI0_SCKCR, DIVSEL_XSPI0, > + sel_clk_pll4d1_div3_div4, > + ARRAY_SIZE(sel_clk_pll4d1_div3_div4), CLK_MUX_HIWORD_MASK), > + DEF_MUX(".divselxspi1", CLK_DIVSELXSPI1_SCKCR, DIVSEL_XSPI1, > + sel_clk_pll4d1_div3_div4, > + ARRAY_SIZE(sel_clk_pll4d1_div3_div4), CLK_MUX_HIWORD_MASK), > + > /* Core output clk */ > DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0, > dtable_1_2), > @@ -178,9 +205,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { > DEF_FIXED("ETCLKC", R9A09G077_ETCLKC, CLK_SEL_CLK_PLL1, 10, 1), > DEF_FIXED("ETCLKD", R9A09G077_ETCLKD, CLK_SEL_CLK_PLL1, 20, 1), > DEF_FIXED("ETCLKE", R9A09G077_ETCLKE, CLK_SEL_CLK_PLL1, 40, 1), > + DEF_DIV("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR, > + FSELXSPI0, dtable_6_8_16_32_64), > + DEF_DIV("XSPI_CLK1", R9A09G077_XSPI_CLK1, CLK_DIVSELXSPI1_SCKCR, > + FSELXSPI1, dtable_6_8_16_32_64), > }; Perhaps we need a custom clock for this? According to Section 7.3.1 "SCKCR : System Clock Control Register", some divider combinations are prohibited: - 4 x 6, - 4 x 32, - 4 x 64. The last two are probably not an issue iff the xSPI driver never tries to set the corresponding clock rates. However, the first one may be an issue, as both 3 x 8 (valid) and 4 x 6 (prohibited) yield the same resulting divider, and I believe we cannot be sure the clock core will never pick the prohibited combination. The rest LGTM. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] clk: renesas: r9a09g077: Add xSPI core and module clocks 2025-10-24 10:08 ` Geert Uytterhoeven @ 2025-10-27 21:04 ` Lad, Prabhakar 0 siblings, 0 replies; 7+ messages in thread From: Lad, Prabhakar @ 2025-10-27 21:04 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-renesas-soc, linux-clk, linux-kernel, devicetree, Biju Das, Fabrizio Castro, Lad Prabhakar Hi Geert, Thank you for the review. On Fri, Oct 24, 2025 at 11:08 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Tue, 14 Oct 2025 at 17:13, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add module and core clocks used by xSPI (Expanded SPI) IP on the > > R9A09G077 SoC. > > > > The xSPI block uses PCLKH as its bus clock, while the operation clock > > (XSPI_CLKn) is derived from PLL4. To support this, define new selectors > > and dividers (FSELXSPI0/1 and DIVSEL_XSPI0/1) in SCKCR. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/drivers/clk/renesas/r9a09g077-cpg.c > > +++ b/drivers/clk/renesas/r9a09g077-cpg.c > > > @@ -105,6 +113,15 @@ static const struct clk_div_table dtable_1_2[] = { > > {0, 0}, > > }; > > > > +static const struct clk_div_table dtable_6_8_16_32_64[] = { > > + {6, 64}, > > + {5, 32}, > > + {4, 16}, > > + {3, 8}, > > + {2, 6}, > > + {0, 0}, > > +}; > > + > > static const struct clk_div_table dtable_24_25_30_32[] = { > > {0, 32}, > > {1, 30}, > > @@ -119,6 +136,7 @@ static const char * const sel_clk_pll0[] = { ".loco", ".pll0" }; > > static const char * const sel_clk_pll1[] = { ".loco", ".pll1" }; > > static const char * const sel_clk_pll2[] = { ".loco", ".pll2" }; > > static const char * const sel_clk_pll4[] = { ".loco", ".pll4" }; > > +static const char * const sel_clk_pll4d1_div3_div4[] = { ".pll4d1_div3", ".pll4d1_div4" }; > > > > static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { > > /* External Clock Inputs */ > > @@ -154,6 +172,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { > > DEF_DIV(".sci5async", CLK_SCI5ASYNC, CLK_PLL4D1, DIVSCI5ASYNC, > > dtable_24_25_30_32), > > > > + DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1), > > + DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1), > > + DEF_MUX(".divselxspi0", CLK_DIVSELXSPI0_SCKCR, DIVSEL_XSPI0, > > + sel_clk_pll4d1_div3_div4, > > + ARRAY_SIZE(sel_clk_pll4d1_div3_div4), CLK_MUX_HIWORD_MASK), > > + DEF_MUX(".divselxspi1", CLK_DIVSELXSPI1_SCKCR, DIVSEL_XSPI1, > > + sel_clk_pll4d1_div3_div4, > > + ARRAY_SIZE(sel_clk_pll4d1_div3_div4), CLK_MUX_HIWORD_MASK), > > + > > /* Core output clk */ > > DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0, > > dtable_1_2), > > @@ -178,9 +205,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { > > DEF_FIXED("ETCLKC", R9A09G077_ETCLKC, CLK_SEL_CLK_PLL1, 10, 1), > > DEF_FIXED("ETCLKD", R9A09G077_ETCLKD, CLK_SEL_CLK_PLL1, 20, 1), > > DEF_FIXED("ETCLKE", R9A09G077_ETCLKE, CLK_SEL_CLK_PLL1, 40, 1), > > + DEF_DIV("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR, > > + FSELXSPI0, dtable_6_8_16_32_64), > > + DEF_DIV("XSPI_CLK1", R9A09G077_XSPI_CLK1, CLK_DIVSELXSPI1_SCKCR, > > + FSELXSPI1, dtable_6_8_16_32_64), > > }; > > Perhaps we need a custom clock for this? > According to Section 7.3.1 "SCKCR : System Clock Control Register", > some divider combinations are prohibited: > - 4 x 6, > - 4 x 32, > - 4 x 64. > The last two are probably not an issue iff the xSPI driver never tries > to set the corresponding clock rates. > However, the first one may be an issue, as both 3 x 8 (valid) and 4 x 6 > (prohibited) yield the same resulting divider, and I believe we cannot > be sure the clock core will never pick the prohibited combination. > Agreed, I think I will have to compose both MUX and the divider into a single clock so that the dividers can be adjusted based on the MUX value, or do you have any suggestion to just adjust the divider clocks and leave the MUX clocks as is? Cheers, Prabhakar ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-10-27 21:05 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-10-14 15:13 [PATCH 0/2] Add XSPI core and module clocks to Renesas R9A09G077/87 SoCs Prabhakar 2025-10-14 15:13 ` [PATCH 1/2] dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs Prabhakar 2025-10-14 17:48 ` Conor Dooley 2025-10-24 10:09 ` Geert Uytterhoeven 2025-10-14 15:13 ` [PATCH 2/2] clk: renesas: r9a09g077: Add xSPI core and module clocks Prabhakar 2025-10-24 10:08 ` Geert Uytterhoeven 2025-10-27 21:04 ` Lad, Prabhakar
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