[PATCH 0/8] Add support for Renesas RZ/N2H (R9A09G087) SoC and RZ/N2H EVK

[PATCH 0/8] Add support for Renesas RZ/N2H (R9A09G087) SoC and RZ/N2H EVK

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series adds support for the Renesas RZ/N2H (R9A09G087) SoC and
the RZ/N2H EVK (R9A09G087M44-RZN2H-EVK) evaluation board. The RZ/N2H SoC
is very much similar to the RZ/T2H (R9A09G077) SoC. 

RZ/N2H is a high-performance MPU that delivers advanced application
processing and real-time operation for industrial applications. It
features a quad-core Arm Cortex-A55 and dual-core Arm Cortex-R52
configuration, with security features, and is designed for real-time
control and high-speed communication.

RZ/N2H SoC supports below features:
- Quad-core Arm Cortex-A55 and dual-core Arm Cortex-R52 configuration
- Security functions (optional)
- Encoder interfaces
  * 16 channels
  * EnDat 2.2, BiSS-C, A-format, and HIPERFACE DSL-compliant interfaces
  * Frequency-divided output from an encoder
- Various communications interfaces
  * Ethernet
    - EtherCAT slave Controller: 3 ports
    - Ethernet switch: 3 ports
    - Ethernet MAC: 1 port x 3 units
  *  USB 2.0 high-speed host/functions: 1 channel
  * CAN/CANFD (compliant with ISO11898-1): 2 channels
  * SCI with 16-byte transmission and reception FIFOs: 6 channels +
    12 channels (for encoder)
  * I2C bus interface: 3 channel for transfer at up to 400 kbps
  * SPI: 4 channels
  * xSPI: 2 channels
  * PCI Express Gen3: 2 lane x 1 port or 1 lane x 2 ports
  * SD card host interface: 2 channels
- Serial host interface
- 12 bits x 3 unit (4 channels for unit 0, 1, 15 channels for unit 2
- LCD Controller
- General-purpose I/O ports
- Trigonometric function unit
- 16-bit x 8 + 32-bit MTU3 (9 channels), 32-bit GPT (56 channels)
- 6-bit CMT (6 channels), 32-bit CMTW (2 channels)

For more information, please refer to the product page:

https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzn2h-advanced-mpu-delivers-high-performance-application-processing-and-real-time-operation-industrial?srsltid=AfmBOoro9kUrZ77ugeURFIlE5ToiFazSyzIsbjBDdGs83NHZfhlkFHlJ

Note, this patch series applies on top of the patch series
- "Add initial support for Renesas RZ/T2H SoC" [1].
- "dt-bindings: serial: renesas,rsci: Document RZ/N2H support" [2].

[1] https://lore.kernel.org/all/20250523142417.2840797-1-thierry.bultel.yh@bp.renesas.com/
[2] https://lore.kernel.org/all/20250609192344.293317-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

Cheers,
Prabhakar

Lad Prabhakar (4):
  soc: renesas: Add config option for RZ/N2H (R9A09G087) SoC
  dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
  clk: renesas: Add MSSR support to RZ/N2H SoC
  arm64: dts: renesas: Add initial SoC DTSI for RZ/N2H SoC

Paul Barker (4):
  dt-bindings: soc: Add Renesas RZ/N2H (R9A09G087) SoC
  arm64: dts: renesas: Refactor RZ/T2H EVK device tree
  arm64: dts: renesas: Add DTSI for R9A09G087M44 variant of RZ/N2H SoC
  arm64: dts: renesas: Add initial support for RZ/N2H EVK

 .../bindings/clock/renesas,cpg-mssr.yaml      |   5 +-
 .../bindings/soc/renesas/renesas.yaml         |  10 ++
 arch/arm64/boot/dts/renesas/Makefile          |   1 +
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    |  17 +--
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi    | 135 ++++++++++++++++++
 .../dts/renesas/r9a09g087m44-rzn2h-evk.dts    |  16 +++
 arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi |  13 ++
 .../boot/dts/renesas/rzt2h-evk-common.dtsi    |  24 ++++
 drivers/clk/renesas/Kconfig                   |   5 +
 drivers/clk/renesas/Makefile                  |   1 +
 drivers/clk/renesas/r9a09g077-cpg.c           |   1 +
 drivers/clk/renesas/renesas-cpg-mssr.c        |   6 +
 drivers/soc/renesas/Kconfig                   |   6 +
 .../clock/renesas,r9a09g087-cpg-mssr.h        |  28 ++++
 14 files changed, 251 insertions(+), 17 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/rzt2h-evk-common.dtsi
 create mode 100644 include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h

-- 
2.49.0

[PATCH 1/8] dt-bindings: soc: Add Renesas RZ/N2H (R9A09G087) SoC

[Prabhakar]

From: Paul Barker <paul.barker.ct@bp.renesas.com>

Add RZ/N2H (R9A09G087), its variants, and the rzn2h-evk evaluation board
in documentation.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../devicetree/bindings/soc/renesas/renesas.yaml       | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index f074b5c35c6f..af715a813755 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -602,6 +602,16 @@ properties:
               - renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security
           - const: renesas,r9a09g077
 
+      - description: RZ/N2H (R9A09G087)
+        items:
+          - enum:
+              - renesas,rzn2h-evk # RZ/N2H Evaluation Board (RTK9RZN2H0S00000BJ)
+          - enum:
+              - renesas,r9a09g087m04 # RZ/N2H with Single Cortex-A55 + Dual Cortex-R52 - no security
+              - renesas,r9a09g087m24 # RZ/N2H with Dual Cortex-A55 + Dual Cortex-R52 - no security
+              - renesas,r9a09g087m44 # RZ/N2H with Quad Cortex-A55 + Dual Cortex-R52 - no security
+          - const: renesas,r9a09g087
+
 additionalProperties: true
 
 ...
-- 
2.49.0

[PATCH 2/8] soc: renesas: Add config option for RZ/N2H (R9A09G087) SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add a new Kconfig option, ARCH_R9A09G087, to enable ARM64 platform support
for the Renesas RZ/N2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/soc/renesas/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 7f4b4088a14e..ba921f5c3aff 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -414,6 +414,12 @@ config ARCH_R9A09G077
 	help
 	  This enables support for the Renesas RZ/T2H SoC variants.
 
+config ARCH_R9A09G087
+	bool "ARM64 Platform support for RZ/N2H"
+	default y if ARCH_RENESAS
+	help
+	  This enables support for the Renesas RZ/N2H SoC variants.
+
 endif # ARM64
 
 if RISCV
-- 
2.49.0

[PATCH 3/8] dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document support for Module Standby and Software Reset found on the
Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset IP
is similar to that found on the RZ/T2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../bindings/clock/renesas,cpg-mssr.yaml      |  5 +++-
 .../clock/renesas,r9a09g087-cpg-mssr.h        | 28 +++++++++++++++++++
 2 files changed, 32 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
index 708ab6bd7d44..bc2fd3761328 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
@@ -53,6 +53,7 @@ properties:
       - renesas,r8a779g0-cpg-mssr # R-Car V4H
       - renesas,r8a779h0-cpg-mssr # R-Car V4M
       - renesas,r9a09g077-cpg-mssr # RZ/T2H
+      - renesas,r9a09g087-cpg-mssr # RZ/N2H
 
   reg:
     minItems: 1
@@ -112,7 +113,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: renesas,r9a09g077-cpg-mssr
+            enum:
+              - renesas,r9a09g077-cpg-mssr
+              - renesas,r9a09g087-cpg-mssr
     then:
       properties:
         reg:
diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
new file mode 100644
index 000000000000..f28166d6015f
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A09G087 CPG Core Clocks */
+#define R9A09G087_CLK_CA55C0		0
+#define R9A09G087_CLK_CA55C1		1
+#define R9A09G087_CLK_CA55C2		2
+#define R9A09G087_CLK_CA55C3		3
+#define R9A09G087_CLK_CA55S		4
+#define R9A09G087_CLK_CR52_CPU0		5
+#define R9A09G087_CLK_CR52_CPU1		6
+#define R9A09G087_CLK_CKIO		7
+#define R9A09G087_CLK_PCLKAH		8
+#define R9A09G087_CLK_PCLKAM		9
+#define R9A09G087_CLK_PCLKAL		10
+#define R9A09G087_CLK_PCLKGPTL		11
+#define R9A09G087_CLK_PCLKH		12
+#define R9A09G087_CLK_PCLKM		13
+#define R9A09G087_CLK_PCLKL		14
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
-- 
2.49.0

[PATCH 4/8] clk: renesas: Add MSSR support to RZ/N2H SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add clock driver support for the Renesas RZ/N2H (R9A09G087) SoC by reusing
the existing RZ/T2H (R9A09G077) CPG/MSSR implementation, as both SoCs
share the same clock and reset architecture.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/Kconfig            | 5 +++++
 drivers/clk/renesas/Makefile           | 1 +
 drivers/clk/renesas/r9a09g077-cpg.c    | 1 +
 drivers/clk/renesas/renesas-cpg-mssr.c | 6 ++++++
 4 files changed, 13 insertions(+)

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 45f9ae5b6ef1..6a5a04664990 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -44,6 +44,7 @@ config CLK_RENESAS
 	select CLK_R9A09G056 if ARCH_R9A09G056
 	select CLK_R9A09G057 if ARCH_R9A09G057
 	select CLK_R9A09G077 if ARCH_R9A09G077
+	select CLK_R9A09G087 if ARCH_R9A09G087
 	select CLK_SH73A0 if ARCH_SH73A0
 
 if CLK_RENESAS
@@ -213,6 +214,10 @@ config CLK_R9A09G077
 	bool "RZ/T2H clock support" if COMPILE_TEST
 	select CLK_RENESAS_CPG_MSSR
 
+config CLK_R9A09G087
+	bool "RZ/N2H clock support" if COMPILE_TEST
+	select CLK_RENESAS_CPG_MSSR
+
 config CLK_SH73A0
 	bool "SH-Mobile AG5 clock support" if COMPILE_TEST
 	select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index d8d894a15d24..d28eb276a153 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_CLK_R9A09G047)		+= r9a09g047-cpg.o
 obj-$(CONFIG_CLK_R9A09G056)		+= r9a09g056-cpg.o
 obj-$(CONFIG_CLK_R9A09G057)		+= r9a09g057-cpg.o
 obj-$(CONFIG_CLK_R9A09G077)		+= r9a09g077-cpg.o
+obj-$(CONFIG_CLK_R9A09G087)		+= r9a09g077-cpg.o
 obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
 
 # Family
diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index 206816a2df23..8002e1672b46 100644
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 
 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
+#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
 #include "renesas-cpg-mssr.h"
 
 #define RZT2H_REG_BLOCK_SHIFT	11
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 4a5ac9eef9cc..5ff6ee1f7d4b 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -941,6 +941,12 @@ static const struct of_device_id cpg_mssr_match[] = {
 		.compatible = "renesas,r9a09g077-cpg-mssr",
 		.data = &r9a09g077_cpg_mssr_info,
 	},
+#endif
+#ifdef CONFIG_CLK_R9A09G087
+	{
+		.compatible = "renesas,r9a09g087-cpg-mssr",
+		.data = &r9a09g077_cpg_mssr_info,
+	},
 #endif
 	{ /* sentinel */ }
 };
-- 
2.49.0

[PATCH 5/8] arm64: dts: renesas: Add initial SoC DTSI for RZ/N2H SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add initial SoC DTSI for Renesas RZ/N2H ("R9A09G087") SoC, below are
the list of blocks added:
- EXT CLKs
- 4X CA55
- SCIF
- CPG
- GIC
- ARMv8 Timer

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 135 +++++++++++++++++++++
 1 file changed, 135 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
new file mode 100644
index 000000000000..c98753775e93
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/N2H SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#define RZN2H_PINS_PER_PORT	8
+
+/*
+ * Create the pin index from its bank and position numbers and store in
+ * the upper 16 bits the alternate function identifier
+ */
+#define RZN2H_PORT_PINMUX(b, p, f)	((b) * RZN2H_PINS_PER_PORT + (p) | ((f) << 16))
+
+/* Convert a port and pin label to its global pin index */
+#define RZN2H_GPIO(port, pin)	((port) * RZN2H_PINS_PER_PORT + (pin))
+
+#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a09g087";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		l3_ca55: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-size = <0x100000>;
+			cache-level = <3>;
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a55";
+			reg = <0>;
+			device_type = "cpu";
+			next-level-cache = <&l3_ca55>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			device_type = "cpu";
+			next-level-cache = <&l3_ca55>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			device_type = "cpu";
+			next-level-cache = <&l3_ca55>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			device_type = "cpu";
+			next-level-cache = <&l3_ca55>;
+			enable-method = "psci";
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		sci0: serial@80005000 {
+			compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
+			reg = <0 0x80005000 0 0x400>;
+			interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+			clock-names = "operation", "bus";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller@80280000 {
+			compatible = "renesas,r9a09g087-cpg-mssr";
+			reg = <0 0x80280000 0 0x1000>,
+			      <0 0x81280000 0 0x9000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		gic: interrupt-controller@83000000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x83000000 0 0x40000>,
+			      <0x0 0x83040000 0 0x160000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+	};
+};
-- 
2.49.0

[PATCH 6/8] arm64: dts: renesas: Refactor RZ/T2H EVK device tree

[Prabhakar]

From: Paul Barker <paul.barker.ct@bp.renesas.com>

The RZ/T2H EVK and RZ/N2H EVK are very similar boards. As there is so
much overlap between these parts, common device tree entries are moved
to the new file rzt2h-evk-common.dtsi.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    | 17 +------------
 .../boot/dts/renesas/rzt2h-evk-common.dtsi    | 24 +++++++++++++++++++
 2 files changed, 25 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/rzt2h-evk-common.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index bbacdca1959e..b5e590be0f95 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -8,24 +8,9 @@
 /dts-v1/;
 
 #include "r9a09g077m44.dtsi"
+#include "rzt2h-evk-common.dtsi"
 
 / {
 	model = "Renesas Development EVK based on r9a09g077m44";
 	compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077";
-
-	aliases {
-		serial0 = &sci0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&extal_clk {
-	clock-frequency = <25000000>;
-};
-
-&sci0 {
-	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/renesas/rzt2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-evk-common.dtsi
new file mode 100644
index 000000000000..dc386dbd432b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzt2h-evk-common.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Common Device Tree Source for the RZ/T2H and RZ/N2H Development EVK boards.
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/ {
+	aliases {
+		serial0 = &sci0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&extal_clk {
+	clock-frequency = <25000000>;
+};
+
+&sci0 {
+	status = "okay";
+};
-- 
2.49.0

[PATCH 7/8] arm64: dts: renesas: Add DTSI for R9A09G087M44 variant of RZ/N2H SoC

[Prabhakar]

From: Paul Barker <paul.barker.ct@bp.renesas.com>

Add the device tree source include file for the R9A09G087M44 variant of the
Renesas RZ/N2H SoC, which features a 4-core configuration.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi
new file mode 100644
index 000000000000..ef0343b53309
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/N2H 4-core SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g087.dtsi"
+
+/ {
+	compatible = "renesas,r9a09g087m44", "renesas,r9a09g087";
+};
-- 
2.49.0

[PATCH 8/8] arm64: dts: renesas: Add initial support for RZ/N2H EVK

[Prabhakar]

From: Paul Barker <paul.barker.ct@bp.renesas.com>

Add an initial devicetree file for the Renesas RZ/N2H Evaluation Board
(EVK).

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile             |  1 +
 .../boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts  | 16 ++++++++++++++++
 2 files changed, 17 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 52d0488cfee3..7779e861bb1e 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb
 dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb
+dtb-$(CONFIG_ARCH_R9A09G087) += r9a09g087m44-rzn2h-evk.dtb
 
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
new file mode 100644
index 000000000000..da0c320a0f35
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/N2H Development EVK board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+#include "r9a09g087m44.dtsi"
+#include "rzt2h-evk-common.dtsi"
+
+/ {
+	model = "Renesas Development EVK based on r9a09g087m44";
+	compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087";
+};
-- 
2.49.0

Re: [PATCH 3/8] dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support

[Conor Dooley]

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On Mon, Jun 09, 2025 at 09:36:51PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Document support for Module Standby and Software Reset found on the
> Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset IP
> is similar to that found on the RZ/T2H SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH 1/8] dt-bindings: soc: Add Renesas RZ/N2H (R9A09G087) SoC

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 409 bytes --]

On Mon, Jun 09, 2025 at 09:36:49PM +0100, Prabhakar wrote:
> From: Paul Barker <paul.barker.ct@bp.renesas.com>
> 
> Add RZ/N2H (R9A09G087), its variants, and the rzn2h-evk evaluation board
> in documentation.
> 
> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH 5/8] arm64: dts: renesas: Add initial SoC DTSI for RZ/N2H SoC

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add initial SoC DTSI for Renesas RZ/N2H ("R9A09G087") SoC, below are
> the list of blocks added:
> - EXT CLKs
> - 4X CA55
> - SCIF
> - CPG
> - GIC
> - ARMv8 Timer
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> @@ -0,0 +1,135 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/N2H SoC
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#define RZN2H_PINS_PER_PORT    8
> +
> +/*
> + * Create the pin index from its bank and position numbers and store in
> + * the upper 16 bits the alternate function identifier
> + */
> +#define RZN2H_PORT_PINMUX(b, p, f)     ((b) * RZN2H_PINS_PER_PORT + (p) | ((f) << 16))
> +
> +/* Convert a port and pin label to its global pin index */
> +#define RZN2H_GPIO(port, pin)  ((port) * RZN2H_PINS_PER_PORT + (pin))

These 3 defines belong in the (future) patch that adds the pinctrl node.

> +       timer {
> +               compatible = "arm,armv8-timer";
> +               interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +                                     <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +                                     <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +                                     <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
> +                                     <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
> +               interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";

Thanks, this brought to my attention that the node in the posted RZ/T2H
patch is wrong ;-)

> +       };
> +};

The rest LGTM, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/8] dt-bindings: soc: Add Renesas RZ/N2H (R9A09G087) SoC

[Geert Uytterhoeven]

On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Paul Barker <paul.barker.ct@bp.renesas.com>
>
> Add RZ/N2H (R9A09G087), its variants, and the rzn2h-evk evaluation board
> in documentation.
>
> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.17.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/8] soc: renesas: Add config option for RZ/N2H (R9A09G087) SoC

[Geert Uytterhoeven]

On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add a new Kconfig option, ARCH_R9A09G087, to enable ARM64 platform support
> for the Renesas RZ/N2H SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.17.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/8] dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support

[Geert Uytterhoeven]

Hi Prabhakar,

Thanks for your patch!

On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document support for Module Standby and Software Reset found on the

the Clock Generator and Module Standby and Software Reset

> Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset IP

Clock Generator and ...

> is similar to that found on the RZ/T2H SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> --- /dev/null
> +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
> @@ -0,0 +1,28 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
> +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* R9A09G087 CPG Core Clocks */
> +#define R9A09G087_CLK_CA55C0           0
> +#define R9A09G087_CLK_CA55C1           1
> +#define R9A09G087_CLK_CA55C2           2
> +#define R9A09G087_CLK_CA55C3           3
> +#define R9A09G087_CLK_CA55S            4
> +#define R9A09G087_CLK_CR52_CPU0                5
> +#define R9A09G087_CLK_CR52_CPU1                6
> +#define R9A09G087_CLK_CKIO             7
> +#define R9A09G087_CLK_PCLKAH           8
> +#define R9A09G087_CLK_PCLKAM           9
> +#define R9A09G087_CLK_PCLKAL           10
> +#define R9A09G087_CLK_PCLKGPTL         11
> +#define R9A09G087_CLK_PCLKH            12
> +#define R9A09G087_CLK_PCLKM            13
> +#define R9A09G087_CLK_PCLKL            14

The RZ/T2H DT bindings file lacks PCLKL, which was probably a harmless
oversight (it can always be added later), as it does exist on RZ/T2H,
too, according to the documentation.

However, given drivers/clk/renesas/r9a09g077-cpg.c has
LAST_DT_CORE_CLK = R9A09G077_CLK_PCLKM,
using R9A09G087_CLK_PCLKL will lead to wrong results.

So either you want to add R9A09G077_CLK_PCLKL and update
LAST_DT_CORE_CLK first, or set LAST_DT_CORE_CLK to R9A09G087_CLK_PCLKL
in this patch.

> +
> +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/8] clk: renesas: Add MSSR support to RZ/N2H SoC

[Geert Uytterhoeven]

Hi Prabhakar,

Thanks for your patch!

s@MSSR support to@CPG/MSSR support for@

On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add clock driver support for the Renesas RZ/N2H (R9A09G087) SoC by reusing
> the existing RZ/T2H (R9A09G077) CPG/MSSR implementation, as both SoCs
> share the same clock and reset architecture.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 6/8] arm64: dts: renesas: Refactor RZ/T2H EVK device tree

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Paul Barker <paul.barker.ct@bp.renesas.com>
>
> The RZ/T2H EVK and RZ/N2H EVK are very similar boards. As there is so
> much overlap between these parts, common device tree entries are moved
> to the new file rzt2h-evk-common.dtsi.
>
> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

>  .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    | 17 +------------

Definitely a good idea! Note that r9a09g077m44-rzt2h-evk.dts does not
exist yet in my tree...

>  .../boot/dts/renesas/rzt2h-evk-common.dtsi    | 24 +++++++++++++++++++
>  2 files changed, 25 insertions(+), 16 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/renesas/rzt2h-evk-common.dtsi

Perhaps call it rzt2h-n2h-evk-common.dtsi, to match the filename
of the documentation?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 7/8] arm64: dts: renesas: Add DTSI for R9A09G087M44 variant of RZ/N2H SoC

[Geert Uytterhoeven]

On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Paul Barker <paul.barker.ct@bp.renesas.com>
>
> Add the device tree source include file for the R9A09G087M44 variant of the
> Renesas RZ/N2H SoC, which features a 4-core configuration.
>
> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 8/8] arm64: dts: renesas: Add initial support for RZ/N2H EVK

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Paul Barker <paul.barker.ct@bp.renesas.com>
>
> Add an initial devicetree file for the Renesas RZ/N2H Evaluation Board
> (EVK).
>
> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!


> --- a/arch/arm64/boot/dts/renesas/Makefile
> +++ b/arch/arm64/boot/dts/renesas/Makefile
> @@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb
>  dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
>
>  dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb

Please insert a blank line here, so group DTBs for the same SoC.

> +dtb-$(CONFIG_ARCH_R9A09G087) += r9a09g087m44-rzn2h-evk.dtb
>
>  dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
>  dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo

The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
with the above fixed.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/8] dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Thu, Jun 12, 2025 at 3:38 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Document support for Module Standby and Software Reset found on the
>
> the Clock Generator and Module Standby and Software Reset
>
Ok, I'll amend the commit message as above.

> > Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset IP
>
> Clock Generator and ...
>
Ok, I'll amend the commit message as above.

> > is similar to that found on the RZ/T2H SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
> > @@ -0,0 +1,28 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * Copyright (C) 2025 Renesas Electronics Corp.
> > + */
> > +
> > +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
> > +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > +/* R9A09G087 CPG Core Clocks */
> > +#define R9A09G087_CLK_CA55C0           0
> > +#define R9A09G087_CLK_CA55C1           1
> > +#define R9A09G087_CLK_CA55C2           2
> > +#define R9A09G087_CLK_CA55C3           3
> > +#define R9A09G087_CLK_CA55S            4
> > +#define R9A09G087_CLK_CR52_CPU0                5
> > +#define R9A09G087_CLK_CR52_CPU1                6
> > +#define R9A09G087_CLK_CKIO             7
> > +#define R9A09G087_CLK_PCLKAH           8
> > +#define R9A09G087_CLK_PCLKAM           9
> > +#define R9A09G087_CLK_PCLKAL           10
> > +#define R9A09G087_CLK_PCLKGPTL         11
> > +#define R9A09G087_CLK_PCLKH            12
> > +#define R9A09G087_CLK_PCLKM            13
> > +#define R9A09G087_CLK_PCLKL            14
>
> The RZ/T2H DT bindings file lacks PCLKL, which was probably a harmless
> oversight (it can always be added later), as it does exist on RZ/T2H,
> too, according to the documentation.
>
> However, given drivers/clk/renesas/r9a09g077-cpg.c has
> LAST_DT_CORE_CLK = R9A09G077_CLK_PCLKM,
> using R9A09G087_CLK_PCLKL will lead to wrong results.
>
> So either you want to add R9A09G077_CLK_PCLKL and update
> LAST_DT_CORE_CLK first, or set LAST_DT_CORE_CLK to R9A09G087_CLK_PCLKL
> in this patch.
>
Actually I already have a patch which includes a couple of fixes and
to the orignal bring up series for T2H + I2C support which adds
R9A09G077_CLK_PCLKL and updates LAST_DT_CORE_CLK. I intend to send
them when the base patches are accepted. As there are no users for
PCLKL in the bringup series this won't cause any issues. Is that OK
with you?

Cheers,
Prabhakar

Re: [PATCH 4/8] clk: renesas: Add MSSR support to RZ/N2H SoC

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Thu, Jun 12, 2025 at 3:38 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> s@MSSR support to@CPG/MSSR support for@
>
Ok, I will update it as above in the next version.

Cheers,
Prabhakar

> On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add clock driver support for the Renesas RZ/N2H (R9A09G087) SoC by reusing
> > the existing RZ/T2H (R9A09G077) CPG/MSSR implementation, as both SoCs
> > share the same clock and reset architecture.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The rest LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Re: [PATCH 6/8] arm64: dts: renesas: Refactor RZ/T2H EVK device tree

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Thu, Jun 12, 2025 at 3:47 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Paul Barker <paul.barker.ct@bp.renesas.com>
> >
> > The RZ/T2H EVK and RZ/N2H EVK are very similar boards. As there is so
> > much overlap between these parts, common device tree entries are moved
> > to the new file rzt2h-evk-common.dtsi.
> >
> > Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> >  .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    | 17 +------------
>
> Definitely a good idea! Note that r9a09g077m44-rzt2h-evk.dts does not
> exist yet in my tree...
>
Yep I have based my patches on top of v10, are we waiting for the
serial driver to be merged in first?

> >  .../boot/dts/renesas/rzt2h-evk-common.dtsi    | 24 +++++++++++++++++++
> >  2 files changed, 25 insertions(+), 16 deletions(-)
> >  create mode 100644 arch/arm64/boot/dts/renesas/rzt2h-evk-common.dtsi
>
> Perhaps call it rzt2h-n2h-evk-common.dtsi, to match the filename
> of the documentation?
>
Agreed, I will rename it. (Note although there are similarities, the
DIP switch settings differ quite a lot. So If you prefer Im OK to go
either ways)

Cheers,
Prabhakar

Re: [PATCH 5/8] arm64: dts: renesas: Add initial SoC DTSI for RZ/N2H SoC

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Thu, Jun 12, 2025 at 3:59 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add initial SoC DTSI for Renesas RZ/N2H ("R9A09G087") SoC, below are
> > the list of blocks added:
> > - EXT CLKs
> > - 4X CA55
> > - SCIF
> > - CPG
> > - GIC
> > - ARMv8 Timer
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> > @@ -0,0 +1,135 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/N2H SoC
> > + *
> > + * Copyright (C) 2025 Renesas Electronics Corp.
> > + */
> > +
> > +#define RZN2H_PINS_PER_PORT    8
> > +
> > +/*
> > + * Create the pin index from its bank and position numbers and store in
> > + * the upper 16 bits the alternate function identifier
> > + */
> > +#define RZN2H_PORT_PINMUX(b, p, f)     ((b) * RZN2H_PINS_PER_PORT + (p) | ((f) << 16))
> > +
> > +/* Convert a port and pin label to its global pin index */
> > +#define RZN2H_GPIO(port, pin)  ((port) * RZN2H_PINS_PER_PORT + (pin))
>
> These 3 defines belong in the (future) patch that adds the pinctrl node.
>
Ok, I'll make it to the later patch.

> > +       timer {
> > +               compatible = "arm,armv8-timer";
> > +               interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > +                                     <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > +                                     <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > +                                     <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
> > +                                     <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
> > +               interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
>
> Thanks, this brought to my attention that the node in the posted RZ/T2H
> patch is wrong ;-)
>
I have some fixup patches for T2H which apply on v10, maybe I'll post them.

Cheers,
Prabhakar

> > +       };
> > +};
>
> The rest LGTM, so with the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
>

Re: [PATCH 3/8] dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support

[Geert Uytterhoeven]

Hi Prabhakar,

On Fri, 13 Jun 2025 at 17:29, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> On Thu, Jun 12, 2025 at 3:38 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Mon, 9 Jun 2025 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Document support for Module Standby and Software Reset found on the
> >
> > the Clock Generator and Module Standby and Software Reset
> >
> Ok, I'll amend the commit message as above.
>
> > > Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset IP
> >
> > Clock Generator and ...
> >
> Ok, I'll amend the commit message as above.
>
> > > is similar to that found on the RZ/T2H SoC.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
> > > @@ -0,0 +1,28 @@
> > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > + *
> > > + * Copyright (C) 2025 Renesas Electronics Corp.
> > > + */
> > > +
> > > +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
> > > +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
> > > +
> > > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > > +
> > > +/* R9A09G087 CPG Core Clocks */
> > > +#define R9A09G087_CLK_CA55C0           0
> > > +#define R9A09G087_CLK_CA55C1           1
> > > +#define R9A09G087_CLK_CA55C2           2
> > > +#define R9A09G087_CLK_CA55C3           3
> > > +#define R9A09G087_CLK_CA55S            4
> > > +#define R9A09G087_CLK_CR52_CPU0                5
> > > +#define R9A09G087_CLK_CR52_CPU1                6
> > > +#define R9A09G087_CLK_CKIO             7
> > > +#define R9A09G087_CLK_PCLKAH           8
> > > +#define R9A09G087_CLK_PCLKAM           9
> > > +#define R9A09G087_CLK_PCLKAL           10
> > > +#define R9A09G087_CLK_PCLKGPTL         11
> > > +#define R9A09G087_CLK_PCLKH            12
> > > +#define R9A09G087_CLK_PCLKM            13
> > > +#define R9A09G087_CLK_PCLKL            14
> >
> > The RZ/T2H DT bindings file lacks PCLKL, which was probably a harmless
> > oversight (it can always be added later), as it does exist on RZ/T2H,
> > too, according to the documentation.
> >
> > However, given drivers/clk/renesas/r9a09g077-cpg.c has
> > LAST_DT_CORE_CLK = R9A09G077_CLK_PCLKM,
> > using R9A09G087_CLK_PCLKL will lead to wrong results.
> >
> > So either you want to add R9A09G077_CLK_PCLKL and update
> > LAST_DT_CORE_CLK first, or set LAST_DT_CORE_CLK to R9A09G087_CLK_PCLKL
> > in this patch.
> >
> Actually I already have a patch which includes a couple of fixes and
> to the orignal bring up series for T2H + I2C support which adds
> R9A09G077_CLK_PCLKL and updates LAST_DT_CORE_CLK. I intend to send
> them when the base patches are accepted. As there are no users for
> PCLKL in the bringup series this won't cause any issues. Is that OK
> with you?

Please include that fix in your v2 series, to avoid any possible
issues with using R9A09G087_CLK_PCLKL.
Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds