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[2001:1c00:3b8a:ea00:c4de:d39d:5f4:c77a]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-60c8290fb73sm7382663a12.35.2025.07.01.06.42.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Jul 2025 06:42:07 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 01 Jul 2025 15:42:06 +0200 Message-Id: Cc: "Konrad Dybcio" , "Bjorn Andersson" , "Michael Turquette" , "Stephen Boyd" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Konrad Dybcio" , <~postmarketos/upstreaming@lists.sr.ht>, , , , , Subject: Re: [PATCH 00/10] Add clock drivers for SM7635 From: "Luca Weiss" To: "Dmitry Baryshkov" X-Mailer: aerc 0.20.1-0-g2ecb8770224a-dirty References: <20250625-sm7635-clocks-v1-0-ca3120e3a80e@fairphone.com> <68056b4a-b1c3-401f-8720-8e0c3cda6249@oss.qualcomm.com> In-Reply-To: On Tue Jul 1, 2025 at 1:16 PM CEST, Dmitry Baryshkov wrote: > On Mon, Jun 30, 2025 at 10:01:35AM +0200, Luca Weiss wrote: >> Hi Konrad, >>=20 >> On Fri Jun 27, 2025 at 5:14 PM CEST, Luca Weiss wrote: >> > On Fri Jun 27, 2025 at 5:10 PM CEST, Konrad Dybcio wrote: >> >> On 6/25/25 11:12 AM, Luca Weiss wrote: >> >>> Document and add the clock drivers for GCC, CAMCC, DISPCC, GPUCC and >> >>> VIDEOCC on the SM7635 SoC. >> >>>=20 >> >>> Signed-off-by: Luca Weiss >> >>> --- >> >>> Luca Weiss (10): >> >>> dt-bindings: clock: qcom: document the SM7635 Global Clock Con= troller >> >>> clk: qcom: Add Global Clock controller (GCC) driver for SM7635 >> >>> dt-bindings: clock: qcom: document the SM7635 Camera Clock Con= troller >> >>> clk: qcom: Add Camera Clock controller (CAMCC) driver for SM76= 35 >> >>> dt-bindings: clock: qcom: document the SM7635 Display Clock Co= ntroller >> >>> clk: qcom: Add Display Clock controller (DISPCC) driver for SM= 7635 >> >>> dt-bindings: clock: qcom: document the SM7635 GPU Clock Contro= ller >> >>> clk: qcom: Add Graphics Clock controller (GPUCC) driver for SM= 7635 >> >>> dt-bindings: clock: qcom: document the SM7635 Video Clock Cont= roller >> >>> clk: qcom: Add Video Clock controller (VIDEOCC) driver for SM7= 635 >> >> >> >> We had a massive yak shaving patchset go in this season, please move >> >> the magic settings in .probe to qcom_cc_driver_data {} >> > >> > Okay cool, I found them >> > https://lore.kernel.org/linux-arm-msm/174970084192.547582.612305407582= 982706.b4-ty@kernel.org/ >>=20 >> For camcc, gpucc and videocc it seems quite simple to follow these >> changes. >>=20 >> For dispcc I don't know what to do with this line. >>=20 >> /* Enable clock gating for MDP clocks */ >> regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); > > Use clk_regs_configure() callback to set this bit. Got it, found an example on the lists. > >>=20 >> Do I just keep the regmap references in this probe function and just >> move the clk_lucid_ole_pll_configure & qcom_branch_set_clk_en to the >> config struct? >>=20 >> And similar for gcc, I can move the qcom_branch_set_clk_en calls there >> but the qcom_cc_register_rcg_dfs needs to be kept. > > Would you mind extnding struct qcom_cc_desc with args to call > qcom_cc_register_rcg_dfs() and call it from qcom_cc_really_probe()? Something like this? Not quite sure when (in what order) this should be called, is that place fine? I'd include a patch then in the v2 of this series. diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index b3838d885db2..d53f290c6121 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -390,6 +390,14 @@ int qcom_cc_really_probe(struct device *dev, goto put_rpm; } =20 + if (desc->dfs_rcgs && desc->num_dfs_rcgs) { + ret =3D qcom_cc_register_rcg_dfs(regmap, + desc->dfs_rcgs, + desc->num_dfs_rcgs); + if (ret) + goto put_rpm; + } + cc->rclks =3D rclks; cc->num_rclks =3D num_clks; =20 diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 0f4b2d40c65c..dbe7ebe5b871 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -43,6 +43,8 @@ struct qcom_cc_desc { size_t num_gdscs; struct clk_hw **clk_hws; size_t num_clk_hws; + const struct clk_rcg_dfs_data *dfs_rcgs; + size_t num_dfs_rcgs; const struct qcom_icc_hws_data *icc_hws; size_t num_icc_hws; unsigned int icc_first_node_id; Regards Luca > >>=20 >> Does that sound okay, or what exactly is the desired outcome of the >> requested changes? >>=20 >> Regards >> Luca >>=20 >> > >> >> >> >> Konrad >>=20