From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADE252701B8 for ; Wed, 25 Feb 2026 15:54:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772034900; cv=none; b=qZT8t3v8SBbKwahKTrAbBlji5hI1MlKn0EDvLZtZGMdjo38Se/Xa2s0dr0l0VWpdBKX0T/0ka+fAOy3bLQMVPumMCqz4nXXzpyGq0oNg03q8MMLLBTzMxrbv+pf/8TvnIPdnixt4rpKdiO47PmYnWZ4FXqYbo1lIPwGCj8BNOus= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772034900; c=relaxed/simple; bh=ge6UTwvXMplsfdme0Epvy2rnYNGulSdprPlOI0qZezw=; h=Mime-Version:Content-Type:Date:Message-Id:Subject:Cc:To:From: References:In-Reply-To; b=Au+orUiZhAW1AESNw5Xc3ES1WL5FWrngvttsE6PBlL62oXvaEoADGkv6AP5psJl8yKvVqIdFcA3Nad7G8RsVvp62h8gPb9pFnp5agYjKX3U43ICuSmXNvpgEwFRGu7OaEYHrSEjt4dN9/MVfWfacL+dRvkHNzUF+qk2AKu8TOJc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=TYNnSyRS; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="TYNnSyRS" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id B6B4CC143F2; Wed, 25 Feb 2026 15:55:11 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 9603A5FDE6; Wed, 25 Feb 2026 15:54:56 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 45B1110368F3E; Wed, 25 Feb 2026 16:54:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772034895; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=pdiq6mn6L4gxkJn25+xNcL5IvX0bPmpsgCBQ2Uh6ltY=; b=TYNnSyRSm0vvWR9fe118q3WyE1KpARLT0IIj9bvMXW5/f531Lt5fhC2BzBgQypo6IHGKXc sCCwhpVReuEqTdgOYdQ79eKkfXCtAcgOpSXNDKvMDvNc6pUBS8UCmppcCjPt5hFBuzFpSk DkM6aARSfRPrPSg24Fl0drbqnYsE7qvMHvRSwxb/1Nu17Yc/+/r0vYJZ/b3dGKQf4yB+/6 ASD/ak+Nw2Ovh+4HRhOWZFFBlg9qhS0QS8oFa0swXyC4PJDah1LRk4Hsc6UePn5KYb5PSt +RgCk7uPPL2seQyctqbVhjacGut0vUY5JZOfncEouaUNZmPXpJ6VXAr/jyZ8fw== Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 25 Feb 2026 16:54:50 +0100 Message-Id: Subject: Re: [PATCH v6 3/8] phy: Add driver for EyeQ5 Ethernet PHY wrapper Cc: "Vladimir Kondratiev" , =?utf-8?q?Gr=C3=A9gory_Clement?= , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Kishon Vijay Abraham I" , "Michael Turquette" , "Stephen Boyd" , "Philipp Zabel" , "Thomas Bogendoerfer" , "Neil Armstrong" , , , , , , =?utf-8?q?Beno=C3=AEt_Monin?= , "Tawfik Bayouk" , "Thomas Petazzoni" , "Luca Ceresoli" To: "Vinod Koul" , =?utf-8?q?Th=C3=A9o_Lebrun?= From: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260127-macb-phy-v6-0-cdd840588188@bootlin.com> <20260127-macb-phy-v6-3-cdd840588188@bootlin.com> In-Reply-To: X-Last-TLS-Session-Version: TLSv1.3 On Wed Feb 25, 2026 at 4:00 PM CET, Vinod Koul wrote: > On 27-01-26, 18:09, Th=C3=A9o Lebrun wrote: >> EyeQ5 embeds a system-controller called OLB. It features many unrelated >> registers, and some of those are registers used to configure the >> integration of the RGMII/SGMII Cadence PHY used by MACB/GEM instances. >>=20 >> Wrap in a neat generic PHY provider, exposing two PHYs with standard >> phy_init() / phy_set_mode() / phy_power_on() operations. > > Is there a dependency of this patch with rest of the series. If not > please post different series for subsystems. ACK. It felt sensible to keep patches close together to understand their reasoning. - clk patches are there because they imply we get a dev->of_node. Without them we don't and therefore the driver is useless. - DTS/MIPS patches are there because they exploit this new driver. They show the first users of this driver. Will split for next revision. >> +static int eq5_phy_init(struct phy *phy) >> +{ >> + struct eq5_phy_inst *inst =3D phy_get_drvdata(phy); >> + struct eq5_phy_private *priv =3D inst->priv; >> + struct device *dev =3D priv->dev; >> + u32 reg; >> + >> + dev_dbg(dev, "phy_init(inst=3D%td)\n", inst - priv->phys); >> + >> + writel(0, inst->gp); >> + writel(0, inst->sgmii); >> + >> + udelay(5); > > This is _same_ as exit. Why not call that routine here and document > why... ACK! Thanks, -- Th=C3=A9o Lebrun, Bootlin Embedded Linux and Kernel engineering https://bootlin.com