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[92.40.202.147]) by smtp.gmail.com with ESMTPSA id 131-20020a1c0289000000b0039c5fb1f592sm1261566wmc.14.2022.06.10.09.25.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jun 2022 09:25:15 -0700 (PDT) References: <20220603134705.11156-1-aidanmacdonald.0x0@gmail.com> <20220609224200.D1E8BC34114@smtp.kernel.org> From: Aidan MacDonald To: Paul Cercueil Cc: Stephen Boyd , mturquette@baylibre.com, linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] clk: ingenic-tcu: Properly enable registers before accessing timers Date: Fri, 10 Jun 2022 17:24:38 +0100 In-reply-to: Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Paul Cercueil writes: > Le ven., juin 10 2022 at 16:43:27 +0100, Aidan MacDonald > a =C3=A9crit : >> Stephen Boyd writes: >>=20 >>> Quoting Aidan MacDonald (2022-06-03 06:47:05) >>>> Access to registers is guarded by ingenic_tcu_{enable,disable}_regs() >>>> so the stop bit can be cleared before accessing a timer channel, but >>>> those functions did not clear the stop bit on SoCs with a global TCU >>>> clock gate. >>>> Testing on the X1000 has revealed that the stop bits must be cleared >>>> _and_ the global TCU clock must be ungated to access timer registers. >>>> Programming manuals for the X1000, JZ4740, and JZ4725B specify this >>>> behavior. If the stop bit isn't cleared, then writes to registers do >>>> not take effect, which can leave clocks with no defined parent when >>>> registered and leave clock tree state out of sync with the hardware, >>>> triggering bugs in downstream drivers relying on TCU clocks. >>>> Fixing this is easy: have ingenic_tcu_{enable,disable}_regs() always >>>> clear the stop bit, regardless of the presence of a global TCU gate. >>>> Signed-off-by: Aidan MacDonald >>>> --- >>> Any Fixes: tag? >> Probably 4f89e4b8f121 ("clk: ingenic: Add driver for the TCU clocks") >> but I don't have docs or hardware to confirm the bug affects the jz4770, >> which is the only other SoC affected by the change. >> I think what caused my problem was my bootloader stopping all the timer >> channels. The stop bits are supposed to be zeroed at reset, so I'd guess >> the jz4770 relied on that and only worked by accident. > > I'll test it on JZ4770 this weekend. > >> I'll send a v2 along shortly. Is it worth CC'ing stable as well? > > If the bug is in jz-5.18 or earlier, yes. > > Cheers, > -Paul Thanks. Guess I'll wait for your test results, though I don't expect any problems.