From: Wolfram Sang <wsa@kernel.org>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks
Date: Mon, 10 Oct 2022 20:34:27 +0200 [thread overview]
Message-ID: <Y0Rls4SgBIaUtzcT@shikoro> (raw)
In-Reply-To: <CAMuHMdXK1Bh=6p_8LL54gJL0nKZ27wQb_wxM0ve0svBDG5X-6w@mail.gmail.com>
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> > Some spaces missing after the commas.
>
> I did it this way to keep the columns a little bit more aligned.
> The alternative is to widen the columns, and adds TABs in all rows...
I see.
> > So, no CLK_SASYNCPER at all because R8A779G0_CLK_SASYNCPERD1 divides
> > PLL5 directly. I don't mind which version we use but I think it should
> > be consistent because the diagram looks the same in the specs. What do
> > you think?
>
> I can add an internal SASYNCPER clock on R-Car S4-8, too.
That would be great!
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next prev parent reply other threads:[~2022-10-10 18:34 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-07 13:09 [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks Geert Uytterhoeven
2022-10-09 21:20 ` Wolfram Sang
2022-10-10 11:15 ` Geert Uytterhoeven
2022-10-10 18:34 ` Wolfram Sang [this message]
2022-10-07 13:10 ` [PATCH 2/5] clk: renesas: r8a779g0: Fix HSCIF parent clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 3/5] clk: renesas: r8a779g0: Add SCIF clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 4/5] clk: renesas: r8a779g0: Add PWM clock Geert Uytterhoeven
2022-10-10 7:46 ` Wolfram Sang
2022-10-07 13:10 ` [PATCH 5/5] clk: renesas: r8a779g0: Add TPU clock Geert Uytterhoeven
2022-10-10 7:46 ` Wolfram Sang
2022-10-07 20:47 ` [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Stephen Boyd
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