Re: [PATCH] clk: imx: gate off peripheral clock slice

[Abel Vesa <abelvesa@kernel.org>]

On 21-10-22 15:46:20, Peng Fan wrote:
> Hi Ahmad,
> 
> > Subject: Re: [PATCH] clk: imx: gate off peripheral clock slice
> > 
> > Hello Peng,
> > 
> > On 22.10.21 15:09, Peng Fan (OSS) wrote:
> > > From: Peng Fan <peng.fan@nxp.com>
> > >
> > > The Peripheral clocks are default enabled when SoC power on, and
> > > bootloader not gate off the clocks when booting Linux Kernel.
> > >
> > > So Linux Kernel is not aware the peripheral clocks are enabled and
> > > still take them as disabled because of enable count is zero.
> > >
> > > Then Peripheral clock's source without clock gated off could be
> > > changed when have assigned-parents in device tree
> > >
> > > However, per i.MX8M* reference mannual, "Peripheral clock slices must
> > > be stopped to change the clock source", so need to gate off the the
> > > peripheral clock when registering the clocks to avoid glitch.
> > 
> > This sounds like a fix that should be backported. If so, could you provide a
> > Fixes: Tag?
> 
> We not see any critical issue without this patch, just to avoid
> any potential risk here. So I not add fix tag here.
> 
> Abel, do you prefer a fixes tag or leave it as is?
> 

Lets put a fixes tag still. That way, it will be backported and
it will probably save someone (who's maybe using an older kernel) a headache.
Plus, it will get in sooner.

> Thanks,
> Peng.
> 
> > 
> > Thanks,
> > Ahmad
> > 
> > >
> > > Tested boot on i.MX8MM/P-EVK board
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > >  drivers/clk/imx/clk-composite-8m.c | 9 ++++++++-
> > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/imx/clk-composite-8m.c
> > > b/drivers/clk/imx/clk-composite-8m.c
> > > index 2dfd6149e528..ee41fbf90589 100644
> > > --- a/drivers/clk/imx/clk-composite-8m.c
> > > +++ b/drivers/clk/imx/clk-composite-8m.c
> > > @@ -184,6 +184,7 @@ struct clk_hw *__imx8m_clk_hw_composite(const
> > char *name,
> > >  	struct clk_mux *mux = NULL;
> > >  	const struct clk_ops *divider_ops;
> > >  	const struct clk_ops *mux_ops;
> > > +	u32 val;
> > >
> > >  	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> > >  	if (!mux)
> > > @@ -216,8 +217,14 @@ struct clk_hw *__imx8m_clk_hw_composite(const
> > char *name,
> > >  		div->width = PCG_PREDIV_WIDTH;
> > >  		divider_ops = &imx8m_clk_composite_divider_ops;
> > >  		mux_ops = &clk_mux_ops;
> > > -		if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED))
> > > +		if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED)) {
> > >  			flags |= CLK_SET_PARENT_GATE;
> > > +			if (!(flags & CLK_IS_CRITICAL)) {
> > > +				val = readl(reg);
> > > +				val &= ~BIT(PCG_CGC_SHIFT);
> > > +				writel(val, reg);
> > > +			}
> > > +		}
> > >  	}
> > >
> > >  	div->lock = &imx_ccm_lock;
> > >
> > 
> > 
> > --
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