* [PATCH AUTOSEL 5.16 01/52] clk: imx: Use div64_ul instead of do_div @ 2022-01-17 16:58 Sasha Levin 2022-01-17 16:58 ` [PATCH AUTOSEL 5.16 02/52] clk: samsung: exynos850: Register clocks early Sasha Levin 2022-01-17 16:58 ` [PATCH AUTOSEL 5.16 12/52] clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB Sasha Levin 0 siblings, 2 replies; 6+ messages in thread From: Sasha Levin @ 2022-01-17 16:58 UTC (permalink / raw) To: linux-kernel, stable Cc: Changcheng Deng, Zeal Robot, Abel Vesa, Sasha Levin, mturquette, sboyd, shawnguo, linux-clk, linux-imx, linux-arm-kernel From: Changcheng Deng <deng.changcheng@zte.com.cn> [ Upstream commit c1b6ad9a902539f9c037b6b3c35cb134c5724022 ] do_div() does a 64-by-32 division. Here the divisor is an unsigned long which on some platforms is 64 bit wide. So use div64_ul instead of do_div to avoid a possible truncation. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20211118080634.165275-1-deng.changcheng@zte.com.cn Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/clk/imx/clk-pllv3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 20ee9611ba6e3..eea32f87c60aa 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -247,7 +247,7 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, div = rate / parent_rate; temp64 = (u64) (rate - div * parent_rate); temp64 *= mfd; - do_div(temp64, parent_rate); + temp64 = div64_ul(temp64, parent_rate); mfn = temp64; temp64 = (u64)parent_rate; @@ -277,7 +277,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, div = rate / parent_rate; temp64 = (u64) (rate - div * parent_rate); temp64 *= mfd; - do_div(temp64, parent_rate); + temp64 = div64_ul(temp64, parent_rate); mfn = temp64; val = readl_relaxed(pll->base); @@ -334,7 +334,7 @@ static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf( /* rate = parent_rate * (mfi + mfn/mfd) */ temp64 = rate - parent_rate * mf.mfi; temp64 *= mf.mfd; - do_div(temp64, parent_rate); + temp64 = div64_ul(temp64, parent_rate); mf.mfn = temp64; } -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH AUTOSEL 5.16 02/52] clk: samsung: exynos850: Register clocks early 2022-01-17 16:58 [PATCH AUTOSEL 5.16 01/52] clk: imx: Use div64_ul instead of do_div Sasha Levin @ 2022-01-17 16:58 ` Sasha Levin 2022-01-17 17:11 ` Krzysztof Kozlowski 2022-01-17 16:58 ` [PATCH AUTOSEL 5.16 12/52] clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB Sasha Levin 1 sibling, 1 reply; 6+ messages in thread From: Sasha Levin @ 2022-01-17 16:58 UTC (permalink / raw) To: linux-kernel, stable Cc: Sam Protsenko, Sylwester Nawrocki, Krzysztof Kozlowski, Sasha Levin, tomasz.figa, cw00.choi, mturquette, sboyd, matthias.bgg, linux-samsung-soc, linux-clk, linux-arm-kernel, linux-mediatek From: Sam Protsenko <semen.protsenko@linaro.org> [ Upstream commit bcda841f9bf2cddcf2f000cba96f2e27f6f2bdbf ] Some clocks must be registered before init calls. For example MCT clock (from CMU_PERI) is needed for MCT timer driver, which is registered with TIMER_OF_DECLARE(). By the time we get to core_initcall() used for clk-exynos850 platform driver init, it's already too late. Inability to get "mct" clock in MCT driver leads to kernel panic, as functions registered with *_OF_DECLARE() can't do deferred calls. MCT timer driver can't be fixed either, as it's acting as a clock source and it's essential to register it in start_kernel() -> time_init(). Let's register CMU_PERI clocks early, using CLK_OF_DECLARE(). CMU_TOP generates clocks needed for CMU_PERI, but it's already registered early. While at it, let's cleanup the code a bit, by extracting everything related to CMU initialization and registration to the separate function. Similar issue was discussed at [1] and addressed in commit 1f7db7bbf031 ("clk: renesas: cpg-mssr: Add early clock support"), as well as in drivers/clk/mediatek/clk-mt2712.c. [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20180829132954.64862-2-chris.brandt@renesas.com/ Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211122144206.23134-1-semen.protsenko@linaro.org Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/clk/samsung/clk-exynos850.c | 70 ++++++++++++++++++++--------- 1 file changed, 49 insertions(+), 21 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index 2294989e244c5..79cce8ba88831 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -60,6 +60,43 @@ static void __init exynos850_init_clocks(struct device_node *np, iounmap(reg_base); } +/** + * exynos850_register_cmu - Register specified Exynos850 CMU domain + * @dev: Device object; may be NULL if this function is not being + * called from platform driver probe function + * @np: CMU device tree node + * @cmu: CMU data + * + * Register specified CMU domain, which includes next steps: + * + * 1. Enable parent clock of @cmu CMU + * 2. Set initial registers configuration for @cmu CMU clocks + * 3. Register @cmu CMU clocks using Samsung clock framework API + */ +static void __init exynos850_register_cmu(struct device *dev, + struct device_node *np, const struct samsung_cmu_info *cmu) +{ + /* Keep CMU parent clock running (needed for CMU registers access) */ + if (cmu->clk_name) { + struct clk *parent_clk; + + if (dev) + parent_clk = clk_get(dev, cmu->clk_name); + else + parent_clk = of_clk_get_by_name(np, cmu->clk_name); + + if (IS_ERR(parent_clk)) { + pr_err("%s: could not find bus clock %s; err = %ld\n", + __func__, cmu->clk_name, PTR_ERR(parent_clk)); + } else { + clk_prepare_enable(parent_clk); + } + } + + exynos850_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs); + samsung_cmu_register_one(np, cmu); +} + /* ---- CMU_TOP ------------------------------------------------------------- */ /* Register Offset definitions for CMU_TOP (0x120e0000) */ @@ -347,10 +384,10 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { static void __init exynos850_cmu_top_init(struct device_node *np) { - exynos850_init_clocks(np, top_clk_regs, ARRAY_SIZE(top_clk_regs)); - samsung_cmu_register_one(np, &top_cmu_info); + exynos850_register_cmu(NULL, np, &top_cmu_info); } +/* Register CMU_TOP early, as it's a dependency for other early domains */ CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", exynos850_cmu_top_init); @@ -615,6 +652,15 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = { .clk_name = "dout_peri_bus", }; +static void __init exynos850_cmu_peri_init(struct device_node *np) +{ + exynos850_register_cmu(NULL, np, &peri_cmu_info); +} + +/* Register CMU_PERI early, as it's needed for MCT timer */ +CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", + exynos850_cmu_peri_init); + /* ---- CMU_CORE ------------------------------------------------------------ */ /* Register Offset definitions for CMU_CORE (0x12000000) */ @@ -779,24 +825,9 @@ static int __init exynos850_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; info = of_device_get_match_data(dev); - exynos850_init_clocks(np, info->clk_regs, info->nr_clk_regs); - samsung_cmu_register_one(np, info); - - /* Keep bus clock running, so it's possible to access CMU registers */ - if (info->clk_name) { - struct clk *bus_clk; - - bus_clk = clk_get(dev, info->clk_name); - if (IS_ERR(bus_clk)) { - pr_err("%s: could not find bus clock %s; err = %ld\n", - __func__, info->clk_name, PTR_ERR(bus_clk)); - } else { - clk_prepare_enable(bus_clk); - } - } + exynos850_register_cmu(dev, dev->of_node, info); return 0; } @@ -806,9 +837,6 @@ static const struct of_device_id exynos850_cmu_of_match[] = { { .compatible = "samsung,exynos850-cmu-hsi", .data = &hsi_cmu_info, - }, { - .compatible = "samsung,exynos850-cmu-peri", - .data = &peri_cmu_info, }, { .compatible = "samsung,exynos850-cmu-core", .data = &core_cmu_info, -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH AUTOSEL 5.16 02/52] clk: samsung: exynos850: Register clocks early 2022-01-17 16:58 ` [PATCH AUTOSEL 5.16 02/52] clk: samsung: exynos850: Register clocks early Sasha Levin @ 2022-01-17 17:11 ` Krzysztof Kozlowski 2022-01-17 19:18 ` Sam Protsenko 0 siblings, 1 reply; 6+ messages in thread From: Krzysztof Kozlowski @ 2022-01-17 17:11 UTC (permalink / raw) To: Sasha Levin, linux-kernel, stable Cc: Sam Protsenko, Sylwester Nawrocki, tomasz.figa, cw00.choi, mturquette, sboyd, matthias.bgg, linux-samsung-soc, linux-clk, linux-arm-kernel, linux-mediatek On 17/01/2022 17:58, Sasha Levin wrote: > From: Sam Protsenko <semen.protsenko@linaro.org> > > [ Upstream commit bcda841f9bf2cddcf2f000cba96f2e27f6f2bdbf ] > > Some clocks must be registered before init calls. For example MCT clock > (from CMU_PERI) is needed for MCT timer driver, which is registered > with TIMER_OF_DECLARE(). By the time we get to core_initcall() used for > clk-exynos850 platform driver init, it's already too late. Inability to > get "mct" clock in MCT driver leads to kernel panic, as functions > registered with *_OF_DECLARE() can't do deferred calls. MCT timer driver > can't be fixed either, as it's acting as a clock source and it's > essential to register it in start_kernel() -> time_init(). > > Let's register CMU_PERI clocks early, using CLK_OF_DECLARE(). CMU_TOP > generates clocks needed for CMU_PERI, but it's already registered early. > > While at it, let's cleanup the code a bit, by extracting everything > related to CMU initialization and registration to the separate function. > > Similar issue was discussed at [1] and addressed in commit 1f7db7bbf031 > ("clk: renesas: cpg-mssr: Add early clock support"), as well as in > drivers/clk/mediatek/clk-mt2712.c. > > [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20180829132954.64862-2-chris.brandt@renesas.com/ > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > Link: https://lore.kernel.org/r/20211122144206.23134-1-semen.protsenko@linaro.org > Signed-off-by: Sasha Levin <sashal@kernel.org> > --- > drivers/clk/samsung/clk-exynos850.c | 70 ++++++++++++++++++++--------- > 1 file changed, 49 insertions(+), 21 deletions(-) > I propose to skip this one. Backporting it to v5.16 does not hurt but also does not bring any benefits for the upstream kernel users. There is no support for mentioned Exynos850 in v5.16. It could have only meaning for some downstream, out-of-tree kernels which apply Exynos850 support on top of v5.16, but then they can just take this patch as well. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH AUTOSEL 5.16 02/52] clk: samsung: exynos850: Register clocks early 2022-01-17 17:11 ` Krzysztof Kozlowski @ 2022-01-17 19:18 ` Sam Protsenko 2022-01-22 18:39 ` Sasha Levin 0 siblings, 1 reply; 6+ messages in thread From: Sam Protsenko @ 2022-01-17 19:18 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Sasha Levin, linux-kernel, stable, Sylwester Nawrocki, tomasz.figa, cw00.choi, mturquette, sboyd, matthias.bgg, linux-samsung-soc, linux-clk, linux-arm-kernel, linux-mediatek On Mon, 17 Jan 2022 at 19:11, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> wrote: > > On 17/01/2022 17:58, Sasha Levin wrote: > > From: Sam Protsenko <semen.protsenko@linaro.org> > > > > [ Upstream commit bcda841f9bf2cddcf2f000cba96f2e27f6f2bdbf ] > > > > Some clocks must be registered before init calls. For example MCT clock > > (from CMU_PERI) is needed for MCT timer driver, which is registered > > with TIMER_OF_DECLARE(). By the time we get to core_initcall() used for > > clk-exynos850 platform driver init, it's already too late. Inability to > > get "mct" clock in MCT driver leads to kernel panic, as functions > > registered with *_OF_DECLARE() can't do deferred calls. MCT timer driver > > can't be fixed either, as it's acting as a clock source and it's > > essential to register it in start_kernel() -> time_init(). > > > > Let's register CMU_PERI clocks early, using CLK_OF_DECLARE(). CMU_TOP > > generates clocks needed for CMU_PERI, but it's already registered early. > > > > While at it, let's cleanup the code a bit, by extracting everything > > related to CMU initialization and registration to the separate function. > > > > Similar issue was discussed at [1] and addressed in commit 1f7db7bbf031 > > ("clk: renesas: cpg-mssr: Add early clock support"), as well as in > > drivers/clk/mediatek/clk-mt2712.c. > > > > [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20180829132954.64862-2-chris.brandt@renesas.com/ > > > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > > Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > > Link: https://lore.kernel.org/r/20211122144206.23134-1-semen.protsenko@linaro.org > > Signed-off-by: Sasha Levin <sashal@kernel.org> > > --- > > drivers/clk/samsung/clk-exynos850.c | 70 ++++++++++++++++++++--------- > > 1 file changed, 49 insertions(+), 21 deletions(-) > > > > I propose to skip this one. > > Backporting it to v5.16 does not hurt but also does not bring any > benefits for the upstream kernel users. There is no support for > mentioned Exynos850 in v5.16. > > It could have only meaning for some downstream, out-of-tree kernels > which apply Exynos850 support on top of v5.16, but then they can just > take this patch as well. > Agreed. DTS patches will be merged only in v5.17, hopefully. Till that time the whole clock driver is floating with no users. That's historical thing -- I didn't have "Ack" to submit board dts at the time, and SoC dts couldn't be applied without users (board dts). So I focused on driver work, isolated. Not much sense to backport something without having real users. > > Best regards, > Krzysztof ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH AUTOSEL 5.16 02/52] clk: samsung: exynos850: Register clocks early 2022-01-17 19:18 ` Sam Protsenko @ 2022-01-22 18:39 ` Sasha Levin 0 siblings, 0 replies; 6+ messages in thread From: Sasha Levin @ 2022-01-22 18:39 UTC (permalink / raw) To: Sam Protsenko Cc: Krzysztof Kozlowski, linux-kernel, stable, Sylwester Nawrocki, tomasz.figa, cw00.choi, mturquette, sboyd, matthias.bgg, linux-samsung-soc, linux-clk, linux-arm-kernel, linux-mediatek On Mon, Jan 17, 2022 at 09:18:43PM +0200, Sam Protsenko wrote: >On Mon, 17 Jan 2022 at 19:11, Krzysztof Kozlowski ><krzysztof.kozlowski@canonical.com> wrote: >> >> On 17/01/2022 17:58, Sasha Levin wrote: >> > From: Sam Protsenko <semen.protsenko@linaro.org> >> > >> > [ Upstream commit bcda841f9bf2cddcf2f000cba96f2e27f6f2bdbf ] >> > >> > Some clocks must be registered before init calls. For example MCT clock >> > (from CMU_PERI) is needed for MCT timer driver, which is registered >> > with TIMER_OF_DECLARE(). By the time we get to core_initcall() used for >> > clk-exynos850 platform driver init, it's already too late. Inability to >> > get "mct" clock in MCT driver leads to kernel panic, as functions >> > registered with *_OF_DECLARE() can't do deferred calls. MCT timer driver >> > can't be fixed either, as it's acting as a clock source and it's >> > essential to register it in start_kernel() -> time_init(). >> > >> > Let's register CMU_PERI clocks early, using CLK_OF_DECLARE(). CMU_TOP >> > generates clocks needed for CMU_PERI, but it's already registered early. >> > >> > While at it, let's cleanup the code a bit, by extracting everything >> > related to CMU initialization and registration to the separate function. >> > >> > Similar issue was discussed at [1] and addressed in commit 1f7db7bbf031 >> > ("clk: renesas: cpg-mssr: Add early clock support"), as well as in >> > drivers/clk/mediatek/clk-mt2712.c. >> > >> > [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20180829132954.64862-2-chris.brandt@renesas.com/ >> > >> > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> >> > Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> >> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> >> > Link: https://lore.kernel.org/r/20211122144206.23134-1-semen.protsenko@linaro.org >> > Signed-off-by: Sasha Levin <sashal@kernel.org> >> > --- >> > drivers/clk/samsung/clk-exynos850.c | 70 ++++++++++++++++++++--------- >> > 1 file changed, 49 insertions(+), 21 deletions(-) >> > >> >> I propose to skip this one. >> >> Backporting it to v5.16 does not hurt but also does not bring any >> benefits for the upstream kernel users. There is no support for >> mentioned Exynos850 in v5.16. >> >> It could have only meaning for some downstream, out-of-tree kernels >> which apply Exynos850 support on top of v5.16, but then they can just >> take this patch as well. >> > >Agreed. DTS patches will be merged only in v5.17, hopefully. Till that >time the whole clock driver is floating with no users. That's >historical thing -- I didn't have "Ack" to submit board dts at the >time, and SoC dts couldn't be applied without users (board dts). So I >focused on driver work, isolated. Not much sense to backport something >without having real users. Dropped, thanks! -- Thanks, Sasha ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH AUTOSEL 5.16 12/52] clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB 2022-01-17 16:58 [PATCH AUTOSEL 5.16 01/52] clk: imx: Use div64_ul instead of do_div Sasha Levin 2022-01-17 16:58 ` [PATCH AUTOSEL 5.16 02/52] clk: samsung: exynos850: Register clocks early Sasha Levin @ 2022-01-17 16:58 ` Sasha Levin 1 sibling, 0 replies; 6+ messages in thread From: Sasha Levin @ 2022-01-17 16:58 UTC (permalink / raw) To: linux-kernel, stable Cc: Martin Blumenstingl, Christian Hewitt, Jerome Brunet, Sasha Levin, narmstrong, mturquette, sboyd, khilman, linux-amlogic, linux-clk, linux-arm-kernel From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [ Upstream commit ff54938dd190d85f740b9bf9dde59b550936b621 ] There are reports that 48kHz audio does not work on the WeTek Play 2 (which uses a GXBB SoC), while 44.1kHz audio works fine on the same board. There are also reports of 48kHz audio working fine on GXL and GXM SoCs, which are using an (almost) identical AIU (audio controller). Experimenting has shown that MPLL0 is causing this problem. In the .dts we have by default: assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; The MPLL0 rate is divisible by 48kHz without remainder and the MPLL1 rate is divisible by 44.1kHz without remainder. Swapping these two clock rates "fixes" 48kHz audio but breaks 44.1kHz audio. Everything looks normal when looking at the info provided by the common clock framework while playing 48kHz audio (via I2S with mclk-fs = 256): mpll_prediv 1 1 0 2000000000 mpll0_div 1 1 0 294909641 mpll0 1 1 0 294909641 cts_amclk_sel 1 1 0 294909641 cts_amclk_div 1 1 0 12287902 cts_amclk 1 1 0 12287902 meson-clk-msr however shows that the actual MPLL0 clock is off by more than 38MHz: mp0_out 333322917 +/-10416Hz The rate seen by meson-clk-msr is very close to what we would get when SDM (the fractional part) was ignored: (2000000000Hz * 16384) / ((16384 * 6) = 333.33MHz If SDM was considered the we should get close to: (2000000000Hz * 16384) / ((16384 * 6) + 12808) = 294.9MHz Further experimenting shows that HHI_MPLL_CNTL7[15] does not have any effect on the rate of MPLL0 as seen my meson-clk-msr (regardless of whether that bit is zero or one the rate is always the same according to meson-clk-msr). Using HHI_MPLL_CNTL[25] on the other hand as SDM_EN results in SDM being considered for the rate output by the hardware. The rate - as seen by meson-clk-msr - matches with what we expect when SDM_EN is enabled (fractional part is being considered, resulting in a 294.9MHz output) or disable (fractional part being ignored, resulting in a 333.33MHz output). Reported-by: Christian Hewitt <christianshewitt@gmail.com> Tested-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20211031135006.1508796-1-martin.blumenstingl@googlemail.com Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/clk/meson/gxbb.c | 44 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index d6eed760327d0..608e0e8ca49a8 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -713,6 +713,35 @@ static struct clk_regmap gxbb_mpll_prediv = { }; static struct clk_regmap gxbb_mpll0_div = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = HHI_MPLL_CNTL, + .shift = 25, + .width = 1, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 16, + .width = 9, + }, + .lock = &meson_clk_lock, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll0_div", + .ops = &meson_clk_mpll_ops, + .parent_hws = (const struct clk_hw *[]) { + &gxbb_mpll_prediv.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap gxl_mpll0_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { .reg_off = HHI_MPLL_CNTL7, @@ -749,7 +778,16 @@ static struct clk_regmap gxbb_mpll0 = { .hw.init = &(struct clk_init_data){ .name = "mpll0", .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll0_div.hw }, + .parent_data = &(const struct clk_parent_data) { + /* + * Note: + * GXL and GXBB have different SDM_EN registers. We + * fallback to the global naming string mechanism so + * mpll0_div picks up the appropriate one. + */ + .name = "mpll0_div", + .index = -1, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, }, @@ -3044,7 +3082,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = { [CLKID_VAPB_1] = &gxbb_vapb_1.hw, [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, [CLKID_VAPB] = &gxbb_vapb.hw, - [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, + [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw, [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, @@ -3439,7 +3477,7 @@ static struct clk_regmap *const gxl_clk_regmaps[] = { &gxbb_mpll0, &gxbb_mpll1, &gxbb_mpll2, - &gxbb_mpll0_div, + &gxl_mpll0_div, &gxbb_mpll1_div, &gxbb_mpll2_div, &gxbb_cts_amclk_div, -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-01-22 18:39 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-01-17 16:58 [PATCH AUTOSEL 5.16 01/52] clk: imx: Use div64_ul instead of do_div Sasha Levin 2022-01-17 16:58 ` [PATCH AUTOSEL 5.16 02/52] clk: samsung: exynos850: Register clocks early Sasha Levin 2022-01-17 17:11 ` Krzysztof Kozlowski 2022-01-17 19:18 ` Sam Protsenko 2022-01-22 18:39 ` Sasha Levin 2022-01-17 16:58 ` [PATCH AUTOSEL 5.16 12/52] clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB Sasha Levin
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