Re: [PATCH] clk: imx8mp: Add missing IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock

Laurent Pinchart
2022-02-20T07:05:08Z

Hi Abel,

On Sun, Feb 20, 2022 at 08:58:50AM +0200, Abel Vesa wrote:
> On 22-02-20 07:19:41, Laurent Pinchart wrote:
> > Hi Abel,
> >
> > Do you think we can get this merged in v5.18 ?
>
> Yes. I'm going to apply it tomorrow.
>
> Sorry for the delay.

No worries at all. Thank you for taking care of it.

> > On Fri, Feb 11, 2022 at 11:13:11AM +0200, Laurent Pinchart wrote:
> > > The IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock derives from the
> > > media_mipi_phy1_ref clock and is gated by the shared media clock gate.
> > > Its identifier is defined in dt-bindings/clock/imx8mp-clock.h but its
> > > definition is missing from the driver. Add it.
> > >
> > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
> > > ---
> > > drivers/clk/imx/clk-imx8mp.c | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> > > index c990ad37882b..f23b92906d3b 100644
> > > --- a/drivers/clk/imx/clk-imx8mp.c
> > > +++ b/drivers/clk/imx/clk-imx8mp.c
> > > @@ -694,6 +694,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
> > > hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix", ccm_base + 0x45d0, 0, &share_count_media);
> > > hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media);
> > > hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media);
> > > + hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT] = imx_clk_hw_gate2_shared2("media_mipi_phy1_ref_root", "media_mipi_phy1_ref", ccm_base + 0x45d0, 0, &share_count_media);
> > > hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base + 0x45d0, 0, &share_count_media);
> > >
> > > hws[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);