Re: [PATCH v2 01/15] dt-bindings: ARM: Mediatek: Add new document bindings of MT8186 clock

Rob Herring
2022-02-25T18:57:40Z

On Mon, Feb 21, 2022 at 09:52:44AM +0800, Chun-Jie Chen wrote:
> This patch adds the new binding documentation for system clock
> and functional clock on Mediatek MT8186.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> .../arm/mediatek/mediatek,mt8186-clock.yaml | 56 +++
> .../mediatek/mediatek,mt8186-sys-clock.yaml | 54 +++
> include/dt-bindings/clock/mt8186-clk.h | 445 ++++++++++++++++++
> 3 files changed, 555 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
> create mode 100644 include/dt-bindings/clock/mt8186-clk.h
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
> new file mode 100644
> index 000000000000..373e8a100da3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Mediatek Functional Clock Controller for MT8186
> +
> +maintainers:
> + - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +description:

You need a '|' to preserve the formatting.

> + The clock architecture in Mediatek like below
> + PLLs -->
> + dividers -->
> + muxes
> + -->
> + clock gate
> +
> + The devices provide clock gate control in different IP blocks.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8186-imp_iic_wrap
> + - mediatek,mt8186-mfgsys
> + - mediatek,mt8186-wpesys
> + - mediatek,mt8186-imgsys1
> + - mediatek,mt8186-imgsys2
> + - mediatek,mt8186-vdecsys
> + - mediatek,mt8186-vencsys
> + - mediatek,mt8186-camsys
> + - mediatek,mt8186-camsys_rawa
> + - mediatek,mt8186-camsys_rawb
> + - mediatek,mt8186-mdpsys
> + - mediatek,mt8186-ipesys
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + imp_iic_wrap: clock-controller@11017000 {
> + compatible = "mediatek,mt8186-imp_iic_wrap";
> + reg = <0x11017000 0x1000>;
> + #clock-cells = <1>;
> + };
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
> new file mode 100644
> index 000000000000..4c071dd66b76
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
> @@ -0,0 +1,54 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Mediatek System Clock Controller for MT8186
> +
> +maintainers:
> + - Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +description:

And here.

With that,

Reviewed-by: Rob Herring <robh@kernel.org>

> + The clock architecture in Mediatek like below
> + PLLs -->
> + dividers -->
> + muxes
> + -->
> + clock gate
> +
> + The apmixedsys provides most of PLLs which generated from SoC 26m.
> + The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
> + The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
> + The mcusys provides mux control to select the clock source in AP MCU.
> + The device nodes also provide the system control capacity for configuration.