Re: [PATCH 1/2] clk: renesas: r8a77990: Add RPC clocks

[Wolfram Sang <wsa@kernel.org>]

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On Tue, Mar 29, 2022 at 11:44:25AM +0200, Geert Uytterhoeven wrote:
> Describe the various clocks used by the SPI Multi I/O Bus Controller
> (RPC-IF) on the R-Car E3 SoC: RPCSRC internal clock, RPC{,D2} clocks
> derived from it, and RPC-IF module clock.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

One minor question, though:

> +	DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
> +
>  	DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),
>  
>  	DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
> @@ -107,6 +110,11 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
>  	DEF_GEN3_SD("sd1",     R8A77990_CLK_SD1,   R8A77990_CLK_SD1H, 0x0078),
>  	DEF_GEN3_SD("sd3",     R8A77990_CLK_SD3,   R8A77990_CLK_SD3H, 0x026c),
>  
> +	DEF_BASE("rpc",		R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC,
> +		 CLK_RPCSRC),
> +	DEF_BASE("rpcd2",	R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
> +		 R8A77990_CLK_RPC),
> +

Any reason the RPC clocks are not grouped together? All other SoCs I
checked have that.


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