From: Wolfram Sang <wsa@kernel.org>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 2/2] clk: renesas: r8a77995: Add RPC clocks
Date: Thu, 7 Apr 2022 08:48:19 +0200 [thread overview]
Message-ID: <Yk6JM6pKjxu90Mtm@ninjato> (raw)
In-Reply-To: <3fd1e886b7737cd0e199603bae81d01be9dcf3aa.1648546700.git.geert+renesas@glider.be>
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On Tue, Mar 29, 2022 at 11:44:26AM +0200, Geert Uytterhoeven wrote:
> Describe the various clocks used by the SPI Multi I/O Bus Controller
> (RPC-IF) on the R-Car D3 SoC: RPCSRC internal clock, RPC{,D2} clocks
> derived from it, and RPC-IF module clock.
>
> The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car
> E3, but uses a different pre-divider for the PLL0 parent. Add a new
> macro to describe it, reusing the existing clock type for R-Car E3.
Maybe add a comment in the header file stating the last paragraph, so it
is obvious the "E3" there is intended? Other than that:
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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prev parent reply other threads:[~2022-04-07 6:48 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-29 9:44 [PATCH 0/2] clk: renesas: r8a7799[05]: Add RPC clocks Geert Uytterhoeven
2022-03-29 9:44 ` [PATCH 1/2] clk: renesas: r8a77990: " Geert Uytterhoeven
2022-04-07 6:46 ` Wolfram Sang
2022-04-11 8:57 ` Geert Uytterhoeven
2022-03-29 9:44 ` [PATCH 2/2] clk: renesas: r8a77995: " Geert Uytterhoeven
2022-04-07 6:48 ` Wolfram Sang [this message]
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