[PATCH v2 0/3] clk: Some Clock Range Fixes

[PATCH v2 0/3] clk: Some Clock Range Fixes

[Maxime Ripard]

Hi,

This fixes one regression for Tegra30 reported by Dmitry, and another issue I
came across while looking at it.

We're also adding a bunch of unit tests to cover those cases.

Let me know what you think,
Maxime

Changes from v1:
  - Removed duplicate documentation

Maxime Ripard (3):
  clk: Initialize orphan req_rate
  clk: test: Test clk_set_rate_range on orphan mux
  clk: Drop the rate range on clk_put

 drivers/clk/clk.c      |  55 ++++++++---
 drivers/clk/clk_test.c | 213 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 254 insertions(+), 14 deletions(-)

-- 
2.35.1

[PATCH v2 1/3] clk: Initialize orphan req_rate

[Maxime Ripard]

When registering a clock that doesn't have a recalc_rate implementation,
and doesn't have its parent registered yet, we initialize the clk_core
rate and req_rate fields to 0.

The rate field is later updated when the parent is registered in
clk_core_reparent_orphans_nolock() using __clk_recalc_rates(), but the
req_rate field is never updated.

This leads to an issue in clk_set_rate_range() and clk_put(), since
those functions will call clk_set_rate with the content of req_rate to
provide drivers with the opportunity to change the rate based on the new
boundaries. In this case, we would call clk_set_rate() with a rate of 0,
effectively enforcing the minimum allowed for this clock whenever we
would call one of those two functions, even though the actual rate might
be within range.

Let's fix this by setting req_rate in clk_core_reparent_orphans_nolock()
with the rate field content just updated by the call to
__clk_recalc_rates().

Fixes: 1c8e600440c7 ("clk: Add rate constraints to clocks")
Reported-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> # T30 Nexus7
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
 drivers/clk/clk.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 9bc8bf434b94..915a2fa363b1 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -3479,6 +3479,19 @@ static void clk_core_reparent_orphans_nolock(void)
 			__clk_set_parent_after(orphan, parent, NULL);
 			__clk_recalc_accuracies(orphan);
 			__clk_recalc_rates(orphan, 0);
+
+			/*
+			 * If the clock doesn't have .recalc_rate (so
+			 * wouldn't affect the parent rate) and is
+			 * orphan when it's registered, the
+			 * __clk_init_parent will set the initial
+			 * req_rate to 0.
+			 *
+			 * req_rate is then used by clk_set_rate_range
+			 * and clk_put to trigger a clk_set_rate call
+			 * whenever the boundaries are modified.
+			 */
+			orphan->req_rate = orphan->rate;
 		}
 	}
 }
-- 
2.35.1

Re: [PATCH v2 1/3] clk: Initialize orphan req_rate

[Stephen Boyd]

Quoting Maxime Ripard (2022-03-25 09:11:42)
> When registering a clock that doesn't have a recalc_rate implementation,
> and doesn't have its parent registered yet, we initialize the clk_core
> rate and req_rate fields to 0.
> 
> The rate field is later updated when the parent is registered in
> clk_core_reparent_orphans_nolock() using __clk_recalc_rates(), but the
> req_rate field is never updated.
> 
> This leads to an issue in clk_set_rate_range() and clk_put(), since
> those functions will call clk_set_rate with the content of req_rate to
> provide drivers with the opportunity to change the rate based on the new
> boundaries. In this case, we would call clk_set_rate() with a rate of 0,
> effectively enforcing the minimum allowed for this clock whenever we
> would call one of those two functions, even though the actual rate might
> be within range.
> 
> Let's fix this by setting req_rate in clk_core_reparent_orphans_nolock()
> with the rate field content just updated by the call to
> __clk_recalc_rates().
> 
> Fixes: 1c8e600440c7 ("clk: Add rate constraints to clocks")
> Reported-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
> Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> # T30 Nexus7
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> ---

Applied to clk-next

[PATCH v2 2/3] clk: test: Test clk_set_rate_range on orphan mux

[Maxime Ripard]

A bug recently affected the Tegra30 where calling clk_set_rate_range()
on a clock would make it change its rate to the minimum.

This was due to the clock in question being a mux that was orphan at
registration, which lead to the clk_core req_rate being 0, and the
clk_set_rate_range() function then calling clk_set_rate() with req_rate,
effectively making that clock running at the minimum rate allowed, even
though the initial rate was within that range.

Make a test suite to create a mux initially orphan, and then make sure
that if our clock rate was initially within a given range, then
enforcing that range won't affect it.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
 drivers/clk/clk_test.c | 105 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)

diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c
index a92600311506..146b1759798e 100644
--- a/drivers/clk/clk_test.c
+++ b/drivers/clk/clk_test.c
@@ -72,6 +72,19 @@ static int clk_dummy_set_rate(struct clk_hw *hw,
 	return 0;
 }
 
+static int clk_dummy_single_set_parent(struct clk_hw *hw, u8 index)
+{
+	if (index >= clk_hw_get_num_parents(hw))
+		return -EINVAL;
+
+	return 0;
+}
+
+static u8 clk_dummy_single_get_parent(struct clk_hw *hw)
+{
+	return 0;
+}
+
 static const struct clk_ops clk_dummy_rate_ops = {
 	.recalc_rate = clk_dummy_recalc_rate,
 	.determine_rate = clk_dummy_determine_rate,
@@ -90,6 +103,11 @@ static const struct clk_ops clk_dummy_minimize_rate_ops = {
 	.set_rate = clk_dummy_set_rate,
 };
 
+static const struct clk_ops clk_dummy_single_parent_ops = {
+	.set_parent = clk_dummy_single_set_parent,
+	.get_parent = clk_dummy_single_get_parent,
+};
+
 static int clk_test_init_with_ops(struct kunit *test, const struct clk_ops *ops)
 {
 	struct clk_dummy_context *ctx;
@@ -239,6 +257,92 @@ static struct kunit_suite clk_test_suite = {
 	.test_cases = clk_test_cases,
 };
 
+struct clk_single_parent_ctx {
+	struct clk_dummy_context parent_ctx;
+	struct clk_hw hw;
+};
+
+static int clk_orphan_transparent_single_parent_mux_test_init(struct kunit *test)
+{
+	struct clk_single_parent_ctx *ctx;
+	struct clk_init_data init = { };
+	const char *parents[] = { "orphan_parent" };
+	int ret;
+
+	ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+	test->priv = ctx;
+
+	init.name = "test_orphan_dummy_parent";
+	init.ops = &clk_dummy_single_parent_ops;
+	init.parent_names = parents;
+	init.num_parents = ARRAY_SIZE(parents);
+	init.flags = CLK_SET_RATE_PARENT;
+	ctx->hw.init = &init;
+
+	ret = clk_hw_register(NULL, &ctx->hw);
+	if (ret)
+		return ret;
+
+	memset(&init, 0, sizeof(init));
+	init.name = "orphan_parent";
+	init.ops = &clk_dummy_rate_ops;
+	ctx->parent_ctx.hw.init = &init;
+	ctx->parent_ctx.rate = DUMMY_CLOCK_INIT_RATE;
+
+	ret = clk_hw_register(NULL, &ctx->parent_ctx.hw);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static void clk_orphan_transparent_single_parent_mux_test_exit(struct kunit *test)
+{
+	struct clk_single_parent_ctx *ctx = test->priv;
+
+	clk_hw_unregister(&ctx->hw);
+	clk_hw_unregister(&ctx->parent_ctx.hw);
+}
+
+/*
+ * Test that a mux-only clock, with an initial rate within a range,
+ * will still have the same rate after the range has been enforced.
+ */
+static void clk_test_orphan_transparent_parent_mux_set_range(struct kunit *test)
+{
+	struct clk_single_parent_ctx *ctx = test->priv;
+	struct clk_hw *hw = &ctx->hw;
+	struct clk *clk = hw->clk;
+	unsigned long rate, new_rate;
+
+	rate = clk_get_rate(clk);
+	KUNIT_ASSERT_GT(test, rate, 0);
+
+	KUNIT_ASSERT_EQ(test,
+			clk_set_rate_range(clk,
+					   ctx->parent_ctx.rate - 1000,
+					   ctx->parent_ctx.rate + 1000),
+			0);
+
+	new_rate = clk_get_rate(clk);
+	KUNIT_ASSERT_GT(test, new_rate, 0);
+	KUNIT_EXPECT_EQ(test, rate, new_rate);
+}
+
+static struct kunit_case clk_orphan_transparent_single_parent_mux_test_cases[] = {
+	KUNIT_CASE(clk_test_orphan_transparent_parent_mux_set_range),
+	{}
+};
+
+static struct kunit_suite clk_orphan_transparent_single_parent_test_suite = {
+	.name = "clk-orphan-transparent-single-parent-test",
+	.init = clk_orphan_transparent_single_parent_mux_test_init,
+	.exit = clk_orphan_transparent_single_parent_mux_test_exit,
+	.test_cases = clk_orphan_transparent_single_parent_mux_test_cases,
+};
+
 /*
  * Test that clk_set_rate_range won't return an error for a valid range
  * and that it will make sure the rate of the clock is within the
@@ -788,6 +892,7 @@ static struct kunit_suite clk_range_minimize_test_suite = {
 
 kunit_test_suites(
 	&clk_test_suite,
+	&clk_orphan_transparent_single_parent_test_suite,
 	&clk_range_test_suite,
 	&clk_range_maximize_test_suite,
 	&clk_range_minimize_test_suite
-- 
2.35.1

Re: [PATCH v2 2/3] clk: test: Test clk_set_rate_range on orphan mux

[Stephen Boyd]

Quoting Maxime Ripard (2022-03-25 09:11:43)
> A bug recently affected the Tegra30 where calling clk_set_rate_range()
> on a clock would make it change its rate to the minimum.
> 
> This was due to the clock in question being a mux that was orphan at
> registration, which lead to the clk_core req_rate being 0, and the
> clk_set_rate_range() function then calling clk_set_rate() with req_rate,
> effectively making that clock running at the minimum rate allowed, even
> though the initial rate was within that range.
> 
> Make a test suite to create a mux initially orphan, and then make sure
> that if our clock rate was initially within a given range, then
> enforcing that range won't affect it.
> 
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> ---

Applied to clk-next

[PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

While the current code will trigger a new clk_set_rate call whenever the
rate boundaries are changed through clk_set_rate_range, this doesn't
occur when clk_put() is called.

However, this is essentially equivalent since, after clk_put()
completes, those boundaries won't be enforced anymore.

Let's add a call to clk_set_rate_range in clk_put to make sure those
rate boundaries are dropped and the clock drivers can react.

Let's also add a few tests to make sure this case is covered.

Fixes: c80ac50cbb37 ("clk: Always set the rate on clk_set_range_rate")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
 drivers/clk/clk.c      |  42 ++++++++++------
 drivers/clk/clk_test.c | 108 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 136 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 915a2fa363b1..91f863b7a824 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2332,19 +2332,15 @@ int clk_set_rate_exclusive(struct clk *clk, unsigned long rate)
 }
 EXPORT_SYMBOL_GPL(clk_set_rate_exclusive);
 
-/**
- * clk_set_rate_range - set a rate range for a clock source
- * @clk: clock source
- * @min: desired minimum clock rate in Hz, inclusive
- * @max: desired maximum clock rate in Hz, inclusive
- *
- * Returns success (0) or negative errno.
- */
-int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
+static int clk_set_rate_range_nolock(struct clk *clk,
+				     unsigned long min,
+				     unsigned long max)
 {
 	int ret = 0;
 	unsigned long old_min, old_max, rate;
 
+	lockdep_assert_held(&prepare_lock);
+
 	if (!clk)
 		return 0;
 
@@ -2357,8 +2353,6 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
 		return -EINVAL;
 	}
 
-	clk_prepare_lock();
-
 	if (clk->exclusive_count)
 		clk_core_rate_unprotect(clk->core);
 
@@ -2402,6 +2396,28 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
 	if (clk->exclusive_count)
 		clk_core_rate_protect(clk->core);
 
+	return ret;
+}
+
+/**
+ * clk_set_rate_range - set a rate range for a clock source
+ * @clk: clock source
+ * @min: desired minimum clock rate in Hz, inclusive
+ * @max: desired maximum clock rate in Hz, inclusive
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
+{
+	int ret;
+
+	if (!clk)
+		return 0;
+
+	clk_prepare_lock();
+
+	ret = clk_set_rate_range_nolock(clk, min, max);
+
 	clk_prepare_unlock();
 
 	return ret;
@@ -4403,9 +4419,7 @@ void __clk_put(struct clk *clk)
 	}
 
 	hlist_del(&clk->clks_node);
-	if (clk->min_rate > clk->core->req_rate ||
-	    clk->max_rate < clk->core->req_rate)
-		clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
+	clk_set_rate_range_nolock(clk, 0, ULONG_MAX);
 
 	owner = clk->core->owner;
 	kref_put(&clk->core->ref, __clk_release);
diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c
index 146b1759798e..b205c329cf32 100644
--- a/drivers/clk/clk_test.c
+++ b/drivers/clk/clk_test.c
@@ -760,9 +760,65 @@ static void clk_range_test_multiple_set_range_rate_maximized(struct kunit *test)
 	clk_put(user1);
 }
 
+/*
+ * Test that if we have several subsequent calls to
+ * clk_set_rate_range(), across multiple users, the core will reevaluate
+ * whether a new rate is needed, including when a user drop its clock.
+ *
+ * With clk_dummy_maximize_rate_ops, this means that the the rate will
+ * trail along the maximum as it evolves.
+ */
+static void clk_range_test_multiple_set_range_rate_put_maximized(struct kunit *test)
+{
+	struct clk_dummy_context *ctx = test->priv;
+	struct clk_hw *hw = &ctx->hw;
+	struct clk *clk = hw->clk;
+	struct clk *user1, *user2;
+	unsigned long rate;
+
+	user1 = clk_hw_get_clk(hw, NULL);
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user1);
+
+	user2 = clk_hw_get_clk(hw, NULL);
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user2);
+
+	KUNIT_ASSERT_EQ(test,
+			clk_set_rate(clk, DUMMY_CLOCK_RATE_2 + 1000),
+			0);
+
+	KUNIT_ASSERT_EQ(test,
+			clk_set_rate_range(user1,
+					   0,
+					   DUMMY_CLOCK_RATE_2),
+			0);
+
+	rate = clk_get_rate(clk);
+	KUNIT_ASSERT_GT(test, rate, 0);
+	KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2);
+
+	KUNIT_ASSERT_EQ(test,
+			clk_set_rate_range(user2,
+					   0,
+					   DUMMY_CLOCK_RATE_1),
+			0);
+
+	rate = clk_get_rate(clk);
+	KUNIT_ASSERT_GT(test, rate, 0);
+	KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
+
+	clk_put(user2);
+
+	rate = clk_get_rate(clk);
+	KUNIT_ASSERT_GT(test, rate, 0);
+	KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2);
+
+	clk_put(user1);
+}
+
 static struct kunit_case clk_range_maximize_test_cases[] = {
 	KUNIT_CASE(clk_range_test_set_range_rate_maximized),
 	KUNIT_CASE(clk_range_test_multiple_set_range_rate_maximized),
+	KUNIT_CASE(clk_range_test_multiple_set_range_rate_put_maximized),
 	{}
 };
 
@@ -877,9 +933,61 @@ static void clk_range_test_multiple_set_range_rate_minimized(struct kunit *test)
 	clk_put(user1);
 }
 
+/*
+ * Test that if we have several subsequent calls to
+ * clk_set_rate_range(), across multiple users, the core will reevaluate
+ * whether a new rate is needed, including when a user drop its clock.
+ *
+ * With clk_dummy_minimize_rate_ops, this means that the the rate will
+ * trail along the minimum as it evolves.
+ */
+static void clk_range_test_multiple_set_range_rate_put_minimized(struct kunit *test)
+{
+	struct clk_dummy_context *ctx = test->priv;
+	struct clk_hw *hw = &ctx->hw;
+	struct clk *clk = hw->clk;
+	struct clk *user1, *user2;
+	unsigned long rate;
+
+	user1 = clk_hw_get_clk(hw, NULL);
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user1);
+
+	user2 = clk_hw_get_clk(hw, NULL);
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user2);
+
+	KUNIT_ASSERT_EQ(test,
+			clk_set_rate_range(user1,
+					   DUMMY_CLOCK_RATE_1,
+					   ULONG_MAX),
+			0);
+
+	rate = clk_get_rate(clk);
+	KUNIT_ASSERT_GT(test, rate, 0);
+	KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
+
+	KUNIT_ASSERT_EQ(test,
+			clk_set_rate_range(user2,
+					   DUMMY_CLOCK_RATE_2,
+					   ULONG_MAX),
+			0);
+
+	rate = clk_get_rate(clk);
+	KUNIT_ASSERT_GT(test, rate, 0);
+	KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2);
+
+	clk_put(user2);
+
+	rate = clk_get_rate(clk);
+	KUNIT_ASSERT_GT(test, rate, 0);
+	KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
+
+	clk_put(user1);
+}
+
 static struct kunit_case clk_range_minimize_test_cases[] = {
 	KUNIT_CASE(clk_range_test_set_range_rate_minimized),
 	KUNIT_CASE(clk_range_test_multiple_set_range_rate_minimized),
+	KUNIT_CASE(clk_range_test_multiple_set_range_rate_put_minimized),
 	{}
 };
 
-- 
2.35.1

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Stephen Boyd]

Quoting Maxime Ripard (2022-03-25 09:11:44)
> While the current code will trigger a new clk_set_rate call whenever the
> rate boundaries are changed through clk_set_rate_range, this doesn't
> occur when clk_put() is called.
> 
> However, this is essentially equivalent since, after clk_put()
> completes, those boundaries won't be enforced anymore.
> 
> Let's add a call to clk_set_rate_range in clk_put to make sure those
> rate boundaries are dropped and the clock drivers can react.
> 
> Let's also add a few tests to make sure this case is covered.
> 
> Fixes: c80ac50cbb37 ("clk: Always set the rate on clk_set_range_rate")
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> ---

Applied to clk-next

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Marek Szyprowski]

Hi,

On 25.03.2022 17:11, Maxime Ripard wrote:
> While the current code will trigger a new clk_set_rate call whenever the
> rate boundaries are changed through clk_set_rate_range, this doesn't
> occur when clk_put() is called.
>
> However, this is essentially equivalent since, after clk_put()
> completes, those boundaries won't be enforced anymore.
>
> Let's add a call to clk_set_rate_range in clk_put to make sure those
> rate boundaries are dropped and the clock drivers can react.
>
> Let's also add a few tests to make sure this case is covered.
>
> Fixes: c80ac50cbb37 ("clk: Always set the rate on clk_set_range_rate")
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>

This patch landed recently in linux-next 20220328 as commit 7dabfa2bc480 
("clk: Drop the rate range on clk_put()"). Sadly it breaks booting of 
the few of my test systems: Samsung ARM 32bit Exynos3250 based Rinato 
board and all Amlogic Meson G12B/SM1 based boards (Odroid C4, N2, Khadas 
VIM3/VIM3l). Rinato hangs always with the following oops:

--->8---

Kernel panic - not syncing: MCT hangs after writing 4 (offset:0x420)
CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.17.0-rc1-00014-g7dabfa2bc480 
#11551
Hardware name: Samsung Exynos (Flattened Device Tree)
  unwind_backtrace from show_stack+0x10/0x14
  show_stack from dump_stack_lvl+0x58/0x70
  dump_stack_lvl from panic+0x10c/0x328
  panic from exynos4_mct_tick_stop+0x0/0x2c
---[ end Kernel panic - not syncing: MCT hangs after writing 4 
(offset:0x420) ]---

--->8---

Amlogic boards hang randomly during early userspace init, usually just 
after loading the driver modules.

Reverting $subject on top of linux-next fixes all those problems.

I will try to analyze it a bit more and if possible provide some more 
useful/meaning full logs later.

> ---
>   drivers/clk/clk.c      |  42 ++++++++++------
>   drivers/clk/clk_test.c | 108 +++++++++++++++++++++++++++++++++++++++++
>   2 files changed, 136 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 915a2fa363b1..91f863b7a824 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -2332,19 +2332,15 @@ int clk_set_rate_exclusive(struct clk *clk, unsigned long rate)
>   }
>   EXPORT_SYMBOL_GPL(clk_set_rate_exclusive);
>   
> -/**
> - * clk_set_rate_range - set a rate range for a clock source
> - * @clk: clock source
> - * @min: desired minimum clock rate in Hz, inclusive
> - * @max: desired maximum clock rate in Hz, inclusive
> - *
> - * Returns success (0) or negative errno.
> - */
> -int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
> +static int clk_set_rate_range_nolock(struct clk *clk,
> +				     unsigned long min,
> +				     unsigned long max)
>   {
>   	int ret = 0;
>   	unsigned long old_min, old_max, rate;
>   
> +	lockdep_assert_held(&prepare_lock);
> +
>   	if (!clk)
>   		return 0;
>   
> @@ -2357,8 +2353,6 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
>   		return -EINVAL;
>   	}
>   
> -	clk_prepare_lock();
> -
>   	if (clk->exclusive_count)
>   		clk_core_rate_unprotect(clk->core);
>   
> @@ -2402,6 +2396,28 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
>   	if (clk->exclusive_count)
>   		clk_core_rate_protect(clk->core);
>   
> +	return ret;
> +}
> +
> +/**
> + * clk_set_rate_range - set a rate range for a clock source
> + * @clk: clock source
> + * @min: desired minimum clock rate in Hz, inclusive
> + * @max: desired maximum clock rate in Hz, inclusive
> + *
> + * Returns success (0) or negative errno.
> + */
> +int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
> +{
> +	int ret;
> +
> +	if (!clk)
> +		return 0;
> +
> +	clk_prepare_lock();
> +
> +	ret = clk_set_rate_range_nolock(clk, min, max);
> +
>   	clk_prepare_unlock();
>   
>   	return ret;
> @@ -4403,9 +4419,7 @@ void __clk_put(struct clk *clk)
>   	}
>   
>   	hlist_del(&clk->clks_node);
> -	if (clk->min_rate > clk->core->req_rate ||
> -	    clk->max_rate < clk->core->req_rate)
> -		clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
> +	clk_set_rate_range_nolock(clk, 0, ULONG_MAX);
>   
>   	owner = clk->core->owner;
>   	kref_put(&clk->core->ref, __clk_release);
> diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c
> index 146b1759798e..b205c329cf32 100644
> --- a/drivers/clk/clk_test.c
> +++ b/drivers/clk/clk_test.c
> @@ -760,9 +760,65 @@ static void clk_range_test_multiple_set_range_rate_maximized(struct kunit *test)
>   	clk_put(user1);
>   }
>   
> +/*
> + * Test that if we have several subsequent calls to
> + * clk_set_rate_range(), across multiple users, the core will reevaluate
> + * whether a new rate is needed, including when a user drop its clock.
> + *
> + * With clk_dummy_maximize_rate_ops, this means that the the rate will
> + * trail along the maximum as it evolves.
> + */
> +static void clk_range_test_multiple_set_range_rate_put_maximized(struct kunit *test)
> +{
> +	struct clk_dummy_context *ctx = test->priv;
> +	struct clk_hw *hw = &ctx->hw;
> +	struct clk *clk = hw->clk;
> +	struct clk *user1, *user2;
> +	unsigned long rate;
> +
> +	user1 = clk_hw_get_clk(hw, NULL);
> +	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user1);
> +
> +	user2 = clk_hw_get_clk(hw, NULL);
> +	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user2);
> +
> +	KUNIT_ASSERT_EQ(test,
> +			clk_set_rate(clk, DUMMY_CLOCK_RATE_2 + 1000),
> +			0);
> +
> +	KUNIT_ASSERT_EQ(test,
> +			clk_set_rate_range(user1,
> +					   0,
> +					   DUMMY_CLOCK_RATE_2),
> +			0);
> +
> +	rate = clk_get_rate(clk);
> +	KUNIT_ASSERT_GT(test, rate, 0);
> +	KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2);
> +
> +	KUNIT_ASSERT_EQ(test,
> +			clk_set_rate_range(user2,
> +					   0,
> +					   DUMMY_CLOCK_RATE_1),
> +			0);
> +
> +	rate = clk_get_rate(clk);
> +	KUNIT_ASSERT_GT(test, rate, 0);
> +	KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
> +
> +	clk_put(user2);
> +
> +	rate = clk_get_rate(clk);
> +	KUNIT_ASSERT_GT(test, rate, 0);
> +	KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2);
> +
> +	clk_put(user1);
> +}
> +
>   static struct kunit_case clk_range_maximize_test_cases[] = {
>   	KUNIT_CASE(clk_range_test_set_range_rate_maximized),
>   	KUNIT_CASE(clk_range_test_multiple_set_range_rate_maximized),
> +	KUNIT_CASE(clk_range_test_multiple_set_range_rate_put_maximized),
>   	{}
>   };
>   
> @@ -877,9 +933,61 @@ static void clk_range_test_multiple_set_range_rate_minimized(struct kunit *test)
>   	clk_put(user1);
>   }
>   
> +/*
> + * Test that if we have several subsequent calls to
> + * clk_set_rate_range(), across multiple users, the core will reevaluate
> + * whether a new rate is needed, including when a user drop its clock.
> + *
> + * With clk_dummy_minimize_rate_ops, this means that the the rate will
> + * trail along the minimum as it evolves.
> + */
> +static void clk_range_test_multiple_set_range_rate_put_minimized(struct kunit *test)
> +{
> +	struct clk_dummy_context *ctx = test->priv;
> +	struct clk_hw *hw = &ctx->hw;
> +	struct clk *clk = hw->clk;
> +	struct clk *user1, *user2;
> +	unsigned long rate;
> +
> +	user1 = clk_hw_get_clk(hw, NULL);
> +	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user1);
> +
> +	user2 = clk_hw_get_clk(hw, NULL);
> +	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user2);
> +
> +	KUNIT_ASSERT_EQ(test,
> +			clk_set_rate_range(user1,
> +					   DUMMY_CLOCK_RATE_1,
> +					   ULONG_MAX),
> +			0);
> +
> +	rate = clk_get_rate(clk);
> +	KUNIT_ASSERT_GT(test, rate, 0);
> +	KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
> +
> +	KUNIT_ASSERT_EQ(test,
> +			clk_set_rate_range(user2,
> +					   DUMMY_CLOCK_RATE_2,
> +					   ULONG_MAX),
> +			0);
> +
> +	rate = clk_get_rate(clk);
> +	KUNIT_ASSERT_GT(test, rate, 0);
> +	KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2);
> +
> +	clk_put(user2);
> +
> +	rate = clk_get_rate(clk);
> +	KUNIT_ASSERT_GT(test, rate, 0);
> +	KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1);
> +
> +	clk_put(user1);
> +}
> +
>   static struct kunit_case clk_range_minimize_test_cases[] = {
>   	KUNIT_CASE(clk_range_test_set_range_rate_minimized),
>   	KUNIT_CASE(clk_range_test_multiple_set_range_rate_minimized),
> +	KUNIT_CASE(clk_range_test_multiple_set_range_rate_put_minimized),
>   	{}
>   };
>   

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2160 bytes --]

Hi Marek,

On Wed, Mar 30, 2022 at 10:06:13AM +0200, Marek Szyprowski wrote:
> On 25.03.2022 17:11, Maxime Ripard wrote:
> > While the current code will trigger a new clk_set_rate call whenever the
> > rate boundaries are changed through clk_set_rate_range, this doesn't
> > occur when clk_put() is called.
> >
> > However, this is essentially equivalent since, after clk_put()
> > completes, those boundaries won't be enforced anymore.
> >
> > Let's add a call to clk_set_rate_range in clk_put to make sure those
> > rate boundaries are dropped and the clock drivers can react.
> >
> > Let's also add a few tests to make sure this case is covered.
> >
> > Fixes: c80ac50cbb37 ("clk: Always set the rate on clk_set_range_rate")
> > Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> 
> This patch landed recently in linux-next 20220328 as commit 7dabfa2bc480 
> ("clk: Drop the rate range on clk_put()"). Sadly it breaks booting of 
> the few of my test systems: Samsung ARM 32bit Exynos3250 based Rinato 
> board and all Amlogic Meson G12B/SM1 based boards (Odroid C4, N2, Khadas 
> VIM3/VIM3l). Rinato hangs always with the following oops:
> 
> --->8---
> 
> Kernel panic - not syncing: MCT hangs after writing 4 (offset:0x420)
> CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.17.0-rc1-00014-g7dabfa2bc480 
> #11551
> Hardware name: Samsung Exynos (Flattened Device Tree)
>   unwind_backtrace from show_stack+0x10/0x14
>   show_stack from dump_stack_lvl+0x58/0x70
>   dump_stack_lvl from panic+0x10c/0x328
>   panic from exynos4_mct_tick_stop+0x0/0x2c
> ---[ end Kernel panic - not syncing: MCT hangs after writing 4 
> (offset:0x420) ]---
> 
> --->8---
> 
> Amlogic boards hang randomly during early userspace init, usually just 
> after loading the driver modules.
> 
> Reverting $subject on top of linux-next fixes all those problems.
> 
> I will try to analyze it a bit more and if possible provide some more 
> useful/meaning full logs later.

I'm not sure what could go wrong there, but if you can figure out the
clock, if it tries to set a new rate and what rate it is, it would be
awesome :)

Maxime

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Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Tony Lindgren]

Hi,

* Maxime Ripard <maxime@cerno.tech> [700101 02:00]:
> Hi Marek,
> 
> On Wed, Mar 30, 2022 at 10:06:13AM +0200, Marek Szyprowski wrote:
> > On 25.03.2022 17:11, Maxime Ripard wrote:
> > > While the current code will trigger a new clk_set_rate call whenever the
> > > rate boundaries are changed through clk_set_rate_range, this doesn't
> > > occur when clk_put() is called.
> > >
> > > However, this is essentially equivalent since, after clk_put()
> > > completes, those boundaries won't be enforced anymore.
> > >
> > > Let's add a call to clk_set_rate_range in clk_put to make sure those
> > > rate boundaries are dropped and the clock drivers can react.
> > >
> > > Let's also add a few tests to make sure this case is covered.
> > >
> > > Fixes: c80ac50cbb37 ("clk: Always set the rate on clk_set_range_rate")
> > > Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> > 
> > This patch landed recently in linux-next 20220328 as commit 7dabfa2bc480 
> > ("clk: Drop the rate range on clk_put()"). Sadly it breaks booting of 
> > the few of my test systems: Samsung ARM 32bit Exynos3250 based Rinato 
> > board and all Amlogic Meson G12B/SM1 based boards (Odroid C4, N2, Khadas 
> > VIM3/VIM3l). Rinato hangs always with the following oops:
> > 
> > --->8---
> > 
> > Kernel panic - not syncing: MCT hangs after writing 4 (offset:0x420)
> > CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.17.0-rc1-00014-g7dabfa2bc480 
> > #11551
> > Hardware name: Samsung Exynos (Flattened Device Tree)
> >   unwind_backtrace from show_stack+0x10/0x14
> >   show_stack from dump_stack_lvl+0x58/0x70
> >   dump_stack_lvl from panic+0x10c/0x328
> >   panic from exynos4_mct_tick_stop+0x0/0x2c
> > ---[ end Kernel panic - not syncing: MCT hangs after writing 4 
> > (offset:0x420) ]---
> > 
> > --->8---
> > 
> > Amlogic boards hang randomly during early userspace init, usually just 
> > after loading the driver modules.
> > 
> > Reverting $subject on top of linux-next fixes all those problems.
> > 
> > I will try to analyze it a bit more and if possible provide some more 
> > useful/meaning full logs later.
> 
> I'm not sure what could go wrong there, but if you can figure out the
> clock, if it tries to set a new rate and what rate it is, it would be
> awesome :)

I'm also seeing clockevent break on omaps as a wrong source clock gets
picked.

It seems the dts assigned-clock-parents no longer works now?

So the following no longer sets omap_32k_fck as the clockevent source:

timer@0 {
	assigned-clocks = <&gpt1_fck>;
	assigned-clock-parents = <&omap_32k_fck>;
};

Regards,

Tony

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

Hi,

On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> * Maxime Ripard <maxime@cerno.tech> [700101 02:00]:
> > Hi Marek,
> > 
> > On Wed, Mar 30, 2022 at 10:06:13AM +0200, Marek Szyprowski wrote:
> > > On 25.03.2022 17:11, Maxime Ripard wrote:
> > > > While the current code will trigger a new clk_set_rate call whenever the
> > > > rate boundaries are changed through clk_set_rate_range, this doesn't
> > > > occur when clk_put() is called.
> > > >
> > > > However, this is essentially equivalent since, after clk_put()
> > > > completes, those boundaries won't be enforced anymore.
> > > >
> > > > Let's add a call to clk_set_rate_range in clk_put to make sure those
> > > > rate boundaries are dropped and the clock drivers can react.
> > > >
> > > > Let's also add a few tests to make sure this case is covered.
> > > >
> > > > Fixes: c80ac50cbb37 ("clk: Always set the rate on clk_set_range_rate")
> > > > Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> > > 
> > > This patch landed recently in linux-next 20220328 as commit 7dabfa2bc480 
> > > ("clk: Drop the rate range on clk_put()"). Sadly it breaks booting of 
> > > the few of my test systems: Samsung ARM 32bit Exynos3250 based Rinato 
> > > board and all Amlogic Meson G12B/SM1 based boards (Odroid C4, N2, Khadas 
> > > VIM3/VIM3l). Rinato hangs always with the following oops:
> > > 
> > > --->8---
> > > 
> > > Kernel panic - not syncing: MCT hangs after writing 4 (offset:0x420)
> > > CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.17.0-rc1-00014-g7dabfa2bc480 
> > > #11551
> > > Hardware name: Samsung Exynos (Flattened Device Tree)
> > >   unwind_backtrace from show_stack+0x10/0x14
> > >   show_stack from dump_stack_lvl+0x58/0x70
> > >   dump_stack_lvl from panic+0x10c/0x328
> > >   panic from exynos4_mct_tick_stop+0x0/0x2c
> > > ---[ end Kernel panic - not syncing: MCT hangs after writing 4 
> > > (offset:0x420) ]---
> > > 
> > > --->8---
> > > 
> > > Amlogic boards hang randomly during early userspace init, usually just 
> > > after loading the driver modules.
> > > 
> > > Reverting $subject on top of linux-next fixes all those problems.
> > > 
> > > I will try to analyze it a bit more and if possible provide some more 
> > > useful/meaning full logs later.
> > 
> > I'm not sure what could go wrong there, but if you can figure out the
> > clock, if it tries to set a new rate and what rate it is, it would be
> > awesome :)
> 
> I'm also seeing clockevent break on omaps as a wrong source clock gets
> picked.
> 
> It seems the dts assigned-clock-parents no longer works now?

That would make some kind of sense, __set_clk_parents calls clk_put on
both the assigned clock and its parent.

Could you see what parent (and why?) it tries to enforce then?

It looks like the gpt1_fck driver might favor another parent for that
rate, which, if it's an invalid configuration, shouldn't really happen?

Maxime

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Tony Lindgren]

* Maxime Ripard <maxime@cerno.tech> [220331 09:52]:
> On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> > It seems the dts assigned-clock-parents no longer works now?
> 
> That would make some kind of sense, __set_clk_parents calls clk_put on
> both the assigned clock and its parent.
> 
> Could you see what parent (and why?) it tries to enforce then?

It picks the other option available for the mux clock that only has
two options. No idea why, but if you have some debug patch in mind I
can give it a try.

> It looks like the gpt1_fck driver might favor another parent for that
> rate, which, if it's an invalid configuration, shouldn't really happen?

Hmm there's a gate clock and a mux clock, there's not really a rate
selection available here for the sources.

Regards,

Tony

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 3443 bytes --]

Hi Tony,

On Thu, Mar 31, 2022 at 06:00:42PM +0300, Tony Lindgren wrote:
> * Maxime Ripard <maxime@cerno.tech> [220331 09:52]:
> > On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> > > It seems the dts assigned-clock-parents no longer works now?
> > 
> > That would make some kind of sense, __set_clk_parents calls clk_put on
> > both the assigned clock and its parent.
> > 
> > Could you see what parent (and why?) it tries to enforce then?
> 
> It picks the other option available for the mux clock that only has
> two options. No idea why, but if you have some debug patch in mind I
> can give it a try.
> 
> > It looks like the gpt1_fck driver might favor another parent for that
> > rate, which, if it's an invalid configuration, shouldn't really happen?
> 
> Hmm there's a gate clock and a mux clock, there's not really a rate
> selection available here for the sources.

If I followed the OMAP driver properly, clk_mux_determine_rate_flags is
doing the heavy lifting, could you run your test with

-- >8 --

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 91f863b7a824..c2ab1be62f96 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -552,6 +552,12 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
 	unsigned long best = 0;
 	struct clk_rate_request parent_req = *req;

+	pr_crit("%s: requested rate %lu\n", __func__, req->rate);
+
+	parent = core->parent;
+	pr_crit("%s: current parent %s\n", __func__, parent->name);
+	pr_crit("%s: current parent rate %lu\n", __func__, clk_core_get_rate_nolock(parent));
+
 	/* if NO_REPARENT flag set, pass through to current parent */
 	if (core->flags & CLK_SET_RATE_NO_REPARENT) {
 		parent = core->parent;
@@ -578,6 +584,11 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
 		if (!parent)
 			continue;

+		pr_crit("%s: Trying parent %s (%lu)\n",
+			__func__,
+			parent->name,
+			clk_core_get_rate_nolock(parent));
+
 		if (core->flags & CLK_SET_RATE_PARENT) {
 			parent_req = *req;
 			ret = __clk_determine_rate(parent->hw, &parent_req);
@@ -603,6 +614,11 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
 	req->best_parent_rate = best;
 	req->rate = best;

+	pr_crit("%s: Best parent %s (%lu)\n",
+		__func__,
+		best_parent->name,
+		best);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(clk_mux_determine_rate_flags);
@@ -2201,8 +2217,12 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
 	if (!core)
 		return 0;

+	pr_crit("%s: rate %lu\n", __func__, req_rate);
+
 	rate = clk_core_req_round_rate_nolock(core, req_rate);

+	pr_crit("%s: rounded rate %lu\n", __func__, req_rate);
+
 	/* bail early if nothing to do */
 	if (rate == clk_core_get_rate_nolock(core))
 		return 0;
@@ -2367,6 +2387,8 @@ static int clk_set_rate_range_nolock(struct clk *clk,
 		goto out;
 	}

+	pr_crit("%s: core req rate %lu\n", __func__, clk->core->req_rate);
+
 	/*
 	 * Since the boundaries have been changed, let's give the
 	 * opportunity to the provider to adjust the clock rate based on
@@ -2385,6 +2407,9 @@ static int clk_set_rate_range_nolock(struct clk *clk,
 	 *   this corner case when determining the rate
 	 */
 	rate = clamp(clk->core->req_rate, min, max);
+
+	pr_crit("%s: clamped rate %lu\n", __func__, rate);
+
 	ret = clk_core_set_rate_nolock(clk->core, rate);
 	if (ret) {
 		/* rollback the changes */

-- >8 --

Thanks!
Maxime

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Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Tony Lindgren]

* Maxime Ripard <maxime@cerno.tech> [220331 15:29]:
> On Thu, Mar 31, 2022 at 06:00:42PM +0300, Tony Lindgren wrote:
> > * Maxime Ripard <maxime@cerno.tech> [220331 09:52]:
> > > On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> > > > It seems the dts assigned-clock-parents no longer works now?
> > > 
> > > That would make some kind of sense, __set_clk_parents calls clk_put on
> > > both the assigned clock and its parent.
> > > 
> > > Could you see what parent (and why?) it tries to enforce then?
> > 
> > It picks the other option available for the mux clock that only has
> > two options. No idea why, but if you have some debug patch in mind I
> > can give it a try.
> > 
> > > It looks like the gpt1_fck driver might favor another parent for that
> > > rate, which, if it's an invalid configuration, shouldn't really happen?
> > 
> > Hmm there's a gate clock and a mux clock, there's not really a rate
> > selection available here for the sources.
> 
> If I followed the OMAP driver properly, clk_mux_determine_rate_flags is
> doing the heavy lifting, could you run your test with

Thanks that produces some interesting output. In the working case with
the $subject patch reverted we have:

[    0.000000] Clocking rate (Crystal/Core/MPU): 26.0/400/600 MHz
[    0.000000] clk_core_set_rate_nolock: rate 960000000
[    0.000000] clk_core_set_rate_nolock: rounded rate 960000000
[    0.000000] clk_core_set_rate_nolock: rate 120000000
[    0.000000] clk_core_set_rate_nolock: rounded rate 120000000
[    0.000000] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000000] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 65535999984741ns
[    0.011779] TI gptimer clockevent: always-on 32768 Hz at /ocp@68000000/target-module@48318000

In the failing case With the $subject patch not reverted, the debug
output goes a bit crazy, see below :)

Regards,

Tony

8< ----------------
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 0
[    0.000000] clk_set_rate_range_nolock: clamped rate 0
[    0.000000] clk_core_set_rate_nolock: rate 0
[    0.000000] clk_core_set_rate_nolock: rounded rate 0
[    0.000000] clk_set_rate_range_nolock: core req rate 0
[    0.000000] clk_set_rate_range_nolock: clamped rate 0
[    0.000000] clk_core_set_rate_nolock: rate 0
[    0.000000] clk_core_set_rate_nolock: rounded rate 0
[    0.000000] clk_set_rate_range_nolock: core req rate 0
[    0.000000] clk_set_rate_range_nolock: clamped rate 0
[    0.000000] clk_core_set_rate_nolock: rate 0
[    0.000000] clk_core_set_rate_nolock: rounded rate 0
[    0.000000] clk_set_rate_range_nolock: core req rate 0
[    0.000000] clk_set_rate_range_nolock: clamped rate 0
[    0.000000] clk_core_set_rate_nolock: rate 0
[    0.000000] clk_core_set_rate_nolock: rounded rate 0
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 0
[    0.000000] clk_set_rate_range_nolock: clamped rate 0
[    0.000000] clk_core_set_rate_nolock: rate 0
[    0.000000] clk_core_set_rate_nolock: rounded rate 0
[    0.000000] clk_set_rate_range_nolock: core req rate 0
[    0.000000] clk_set_rate_range_nolock: clamped rate 0
[    0.000000] clk_core_set_rate_nolock: rate 0
[    0.000000] clk_core_set_rate_nolock: rounded rate 0
[    0.000000] clk_set_rate_range_nolock: core req rate 0
[    0.000000] clk_set_rate_range_nolock: clamped rate 0
[    0.000000] clk_core_set_rate_nolock: rate 0
[    0.000000] clk_core_set_rate_nolock: rounded rate 0
[    0.000000] clk_set_rate_range_nolock: core req rate 0
[    0.000000] clk_set_rate_range_nolock: clamped rate 0
[    0.000000] clk_core_set_rate_nolock: rate 0
[    0.000000] clk_core_set_rate_nolock: rounded rate 0
[    0.000000] clk_set_rate_range_nolock: core req rate 0
[    0.000000] clk_set_rate_range_nolock: clamped rate 0
[    0.000000] clk_core_set_rate_nolock: rate 0
[    0.000000] clk_core_set_rate_nolock: rounded rate 0
[    0.000000] clk_set_rate_range_nolock: core req rate 0
[    0.000000] clk_set_rate_range_nolock: clamped rate 0
[    0.000000] clk_core_set_rate_nolock: rate 0
[    0.000000] clk_core_set_rate_nolock: rounded rate 0
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 32768
[    0.000000] clk_set_rate_range_nolock: clamped rate 32768
[    0.000000] clk_core_set_rate_nolock: rate 32768
[    0.000000] clk_core_set_rate_nolock: rounded rate 32768
[    0.000000] clk_set_rate_range_nolock: core req rate 12000000
[    0.000000] clk_set_rate_range_nolock: clamped rate 12000000
[    0.000000] clk_core_set_rate_nolock: rate 12000000
[    0.000000] clk_core_set_rate_nolock: rounded rate 12000000
[    0.000000] clk_set_rate_range_nolock: core req rate 13000000
[    0.000000] clk_set_rate_range_nolock: clamped rate 13000000
[    0.000000] clk_core_set_rate_nolock: rate 13000000
[    0.000000] clk_core_set_rate_nolock: rounded rate 13000000
[    0.000000] clk_set_rate_range_nolock: core req rate 19200000
[    0.000000] clk_set_rate_range_nolock: clamped rate 19200000
[    0.000000] clk_core_set_rate_nolock: rate 19200000
[    0.000000] clk_core_set_rate_nolock: rounded rate 19200000
[    0.000000] clk_set_rate_range_nolock: core req rate 26000000
[    0.000000] clk_set_rate_range_nolock: clamped rate 26000000
[    0.000000] clk_core_set_rate_nolock: rate 26000000
[    0.000000] clk_core_set_rate_nolock: rounded rate 26000000
[    0.000000] clk_set_rate_range_nolock: core req rate 38400000
[    0.000000] clk_set_rate_range_nolock: clamped rate 38400000
[    0.000000] clk_core_set_rate_nolock: rate 38400000
[    0.000000] clk_core_set_rate_nolock: rounded rate 38400000
[    0.000000] clk_set_rate_range_nolock: core req rate 16800000
[    0.000000] clk_set_rate_range_nolock: clamped rate 16800000
[    0.000000] clk_core_set_rate_nolock: rate 16800000
[    0.000000] clk_core_set_rate_nolock: rounded rate 16800000
[    0.000000] clk_set_rate_range_nolock: core req rate 12000000
[    0.000000] clk_set_rate_range_nolock: clamped rate 12000000
[    0.000000] clk_core_set_rate_nolock: rate 12000000
[    0.000000] clk_core_set_rate_nolock: rounded rate 12000000
[    0.000000] clk_set_rate_range_nolock: core req rate 13000000
[    0.000000] clk_set_rate_range_nolock: clamped rate 13000000
[    0.000000] clk_core_set_rate_nolock: rate 13000000
[    0.000000] clk_core_set_rate_nolock: rounded rate 13000000
[    0.000000] clk_set_rate_range_nolock: core req rate 19200000
[    0.000000] clk_set_rate_range_nolock: clamped rate 19200000
[    0.000000] clk_core_set_rate_nolock: rate 19200000
[    0.000000] clk_core_set_rate_nolock: rounded rate 19200000
[    0.000000] clk_set_rate_range_nolock: core req rate 26000000
[    0.000000] clk_set_rate_range_nolock: clamped rate 26000000
[    0.000000] clk_core_set_rate_nolock: rate 26000000
[    0.000000] clk_core_set_rate_nolock: rounded rate 26000000
[    0.000000] clk_set_rate_range_nolock: core req rate 38400000
[    0.000000] clk_set_rate_range_nolock: clamped rate 38400000
[    0.000000] clk_core_set_rate_nolock: rate 38400000
[    0.000000] clk_core_set_rate_nolock: rounded rate 38400000
[    0.000000] clk_set_rate_range_nolock: core req rate 16800000
[    0.000000] clk_set_rate_range_nolock: clamped rate 16800000
[    0.000000] clk_core_set_rate_nolock: rate 16800000
[    0.000000] clk_core_set_rate_nolock: rounded rate 16800000
[    0.000000] clk_set_rate_range_nolock: core req rate 26000000
[    0.000000] clk_set_rate_range_nolock: clamped rate 26000000
[    0.000000] clk_core_set_rate_nolock: rate 26000000
[    0.000000] clk_mux_determine_rate_flags: requested rate 26000000
[    0.000000] clk_mux_determine_rate_flags: current parent virt_26000000_ck
[    0.000000] clk_mux_determine_rate_flags: current parent rate 26000000
[    0.000000] 8<--- cut here ---
[    0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000
[    0.000000] [00000000] *pgd=00000000
[    0.000000] Internal error: Oops: 5 [#1] SMP ARM
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.17.0-13433-g14667a708872 #193
[    0.000000] Hardware name: Generic OMAP36xx (Flattened Device Tree)
[    0.000000] PC is at clk_mux_determine_rate_flags+0x284/0x2dc
[    0.000000] LR is at clk_mux_determine_rate_flags+0x9c/0x2dc
[    0.000000] pc : [<c0a3e28c>]    lr : [<c0a3e0a4>]    psr: 600000d3
[    0.000000] sp : c0f01e68  ip : 3ffff7ff  fp : c0b49f04
[    0.000000] r10: c0b49ef8  r9 : c18843c0  r8 : c18843c0
[    0.000000] r7 : c0f01eb0  r6 : 018cba80  r5 : 00000000  r4 : 018cba80
[    0.000000] r3 : 00000000  r2 : 00000000  r1 : c0f01d38  r0 : c0c923e8
[    0.000000] Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment none
[    0.000000] Control: 10c5387d  Table: 80004019  DAC: 00000051
[    0.000000] Register r0 information: non-slab/vmalloc memory
[    0.000000] Register r1 information: non-slab/vmalloc memory
[    0.000000] Register r2 information: NULL pointer
[    0.000000] Register r3 information: NULL pointer
[    0.000000] Register r4 information: non-paged memory
[    0.000000] Register r5 information: NULL pointer
[    0.000000] Register r6 information: non-paged memory
[    0.000000] Register r7 information: non-slab/vmalloc memory
[    0.000000] Register r8 information: slab kmalloc-192 start c18843c0 pointer offset 0 size 192
[    0.000000] Register r9 information: slab kmalloc-192 start c18843c0 pointer offset 0 size 192
[    0.000000] Register r10 information: non-slab/vmalloc memory
[    0.000000] Register r11 information: non-slab/vmalloc memory
[    0.000000] Register r12 information: non-paged memory
[    0.000000] Process swapper/0 (pid: 0, stack limit = 0x(ptrval))
[    0.000000] Stack: (0xc0f01e68 to 0xc0f02000)
[    0.000000] 1e60:                   00000000 ffffffff 018cba80 00000000 ffffffff 018cba80
[    0.000000] 1e80: c180adc0 c0f051c8 c18843c0 c18843c0 00000000 018cba80 00000000 ffffffff
[    0.000000] 1ea0: c18843c0 c7c9fae8 c7c9fb54 c0a3e378 018cba80 00000000 ffffffff 018cba80
[    0.000000] 1ec0: c180adc0 c0f051c8 c1028c80 c180aa40 018cba80 018cba80 00000000 c065349c
[    0.000000] 1ee0: 00000000 00000000 c7c9fb54 00000000 c180aa40 c180aa40 c180aa80 c0f01f24
[    0.000000] 1f00: c180aac0 00000000 00000001 c0653720 00000000 c180aa80 c0f01f24 c0e2c1a0
[    0.000000] 1f20: 00000000 c180a788 c1880b48 c7c9f940 00000000 00000000 00000000 c7cd0d98
[    0.000000] 1f40: c0e69b50 c0f01f70 a00000d3 c082c740 c7ca0c00 c0e69b50 c0f051c0 c7dffa40
[    0.000000] 1f60: ffffffff 00000000 10c5387d c0e0f6dc 00000000 c0f051c8 ffffffff c100843c
[    0.000000] 1f80: c0e5ba60 c0f051c0 c7dffa40 ffffffff 00000000 10c5387d 00000000 c0e0ba4c
[    0.000000] 1fa0: c1008000 c0e10e7c c1008000 c0e00f80 ffffffff ffffffff 00000000 c0e00728
[    0.000000] 1fc0: 00000000 c0e5ba60 a5aa33e0 c0f051c8 00000000 c0e004bc 00000051 10c0387d
[    0.000000] 1fe0: ffffffff 86feb000 413fc082 10c5387d 00000000 00000000 00000000 00000000
[    0.000000]  clk_mux_determine_rate_flags from clk_core_set_rate_nolock.part.0+0x84/0x1a8
[    0.000000]  clk_core_set_rate_nolock.part.0 from clk_set_rate_range_nolock.part.0+0x278/0x2a0
[    0.000000]  clk_set_rate_range_nolock.part.0 from __clk_put+0x58/0x160
[    0.000000]  __clk_put from of_clk_init+0x1b4/0x268
[    0.000000]  of_clk_init from omap_clk_init+0x38/0x58
[    0.000000]  omap_clk_init from omap_init_time_of+0x8/0x10
[    0.000000]  omap_init_time_of from start_kernel+0x480/0x6b0
[    0.000000]  start_kernel from 0x0
[    0.000000] Code: 0a000008 e587400c e5874000 e59f0050 (e5952000) 
[    0.000000] ---[ end trace 0000000000000000 ]---
[    0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
[    0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Stephen Boyd]

Quoting Tony Lindgren (2022-03-31 10:00:09)
> * Maxime Ripard <maxime@cerno.tech> [220331 15:29]:
> > On Thu, Mar 31, 2022 at 06:00:42PM +0300, Tony Lindgren wrote:
> > > * Maxime Ripard <maxime@cerno.tech> [220331 09:52]:
> > > > On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> > > > > It seems the dts assigned-clock-parents no longer works now?
> > > > 
> > > > That would make some kind of sense, __set_clk_parents calls clk_put on
> > > > both the assigned clock and its parent.
> > > > 
> > > > Could you see what parent (and why?) it tries to enforce then?
> > > 
> > > It picks the other option available for the mux clock that only has
> > > two options. No idea why, but if you have some debug patch in mind I
> > > can give it a try.
> > > 
> > > > It looks like the gpt1_fck driver might favor another parent for that
> > > > rate, which, if it's an invalid configuration, shouldn't really happen?
> > > 
> > > Hmm there's a gate clock and a mux clock, there's not really a rate
> > > selection available here for the sources.
> > 
> > If I followed the OMAP driver properly, clk_mux_determine_rate_flags is
> > doing the heavy lifting, could you run your test with
> 
> Thanks that produces some interesting output. In the working case with
> the $subject patch reverted we have:

I don't think clk_put() dropping a range request is very important right
now. If this isn't fixed tomorrow then we should revert out this patch
so systems can boot -rc1 and try to fix it in parallel.

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1838 bytes --]

Hi,

On Thu, Mar 31, 2022 at 02:58:17PM -0700, Stephen Boyd wrote:
> Quoting Tony Lindgren (2022-03-31 10:00:09)
> > * Maxime Ripard <maxime@cerno.tech> [220331 15:29]:
> > > On Thu, Mar 31, 2022 at 06:00:42PM +0300, Tony Lindgren wrote:
> > > > * Maxime Ripard <maxime@cerno.tech> [220331 09:52]:
> > > > > On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> > > > > > It seems the dts assigned-clock-parents no longer works now?
> > > > > 
> > > > > That would make some kind of sense, __set_clk_parents calls clk_put on
> > > > > both the assigned clock and its parent.
> > > > > 
> > > > > Could you see what parent (and why?) it tries to enforce then?
> > > > 
> > > > It picks the other option available for the mux clock that only has
> > > > two options. No idea why, but if you have some debug patch in mind I
> > > > can give it a try.
> > > > 
> > > > > It looks like the gpt1_fck driver might favor another parent for that
> > > > > rate, which, if it's an invalid configuration, shouldn't really happen?
> > > > 
> > > > Hmm there's a gate clock and a mux clock, there's not really a rate
> > > > selection available here for the sources.
> > > 
> > > If I followed the OMAP driver properly, clk_mux_determine_rate_flags is
> > > doing the heavy lifting, could you run your test with
> > 
> > Thanks that produces some interesting output. In the working case with
> > the $subject patch reverted we have:
> 
> I don't think clk_put() dropping a range request is very important right
> now. If this isn't fixed tomorrow then we should revert out this patch
> so systems can boot -rc1 and try to fix it in parallel.

Yeah, it can definitely be reverted. I'm not so sure that the issue is
with this patch itself though but more that it now triggers a fault
reliably.

Maxime

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Stephen Boyd]

Quoting Maxime Ripard (2022-04-01 05:28:39)
> Hi,
> 
> On Thu, Mar 31, 2022 at 02:58:17PM -0700, Stephen Boyd wrote:
> > 
> > I don't think clk_put() dropping a range request is very important right
> > now. If this isn't fixed tomorrow then we should revert out this patch
> > so systems can boot -rc1 and try to fix it in parallel.
> 
> Yeah, it can definitely be reverted. I'm not so sure that the issue is
> with this patch itself though but more that it now triggers a fault
> reliably.
> 

I don't see a revert sent yet so I'll send one now.

Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Alexander Stein]

Hello,

Am Donnerstag, 31. März 2022, 17:31:34 CEST schrieb Maxime Ripard:
> * PGP Signed by an unknown key
> 
> Hi Tony,
> 
> On Thu, Mar 31, 2022 at 06:00:42PM +0300, Tony Lindgren wrote:
> > * Maxime Ripard <maxime@cerno.tech> [220331 09:52]:
> > > On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> > > > It seems the dts assigned-clock-parents no longer works now?
> > > 
> > > That would make some kind of sense, __set_clk_parents calls clk_put on
> > > both the assigned clock and its parent.
> > > 
> > > Could you see what parent (and why?) it tries to enforce then?
> > 
> > It picks the other option available for the mux clock that only has
> > two options. No idea why, but if you have some debug patch in mind I
> > can give it a try.
> > 
> > > It looks like the gpt1_fck driver might favor another parent for that
> > > rate, which, if it's an invalid configuration, shouldn't really happen?
> > 
> > Hmm there's a gate clock and a mux clock, there's not really a rate
> > selection available here for the sources.
> 
> If I followed the OMAP driver properly, clk_mux_determine_rate_flags is
> doing the heavy lifting, could you run your test with

I'm affected by this patch as well on an imx8mp platform (see [1] for some 
details)

In the failing case with with your patch applied I get the following error 
---
[    0.661064] clk_set_rate_range_nolock: core req rate 500000000                                                                    
[    0.664084] clk_set_rate_range_nolock: clamped rate 500000000                                                                     
[    0.669851] clk_core_set_rate_nolock: rate 500000000                                                                              
[    0.674843] clk_core_set_rate_nolock: rounded rate 500000000                                                                      
[    0.680536] clk_set_rate_range_nolock: core req rate 800000000                                                                    
[    0.686389] clk_set_rate_range_nolock: clamped rate 800000000                                                                     
[    0.692164] clk_core_set_rate_nolock: rate 800000000                                                                              
[    0.697153] clk_mux_determine_rate_flags: requested rate 800000000                                                                
[    0.703363] clk_mux_determine_rate_flags: current parent sys_pll1                                                                 
[    0.709487] clk_mux_determine_rate_flags: current parent rate 800000000                                                           
[    0.716147] Unable to handle kernel NULL pointer dereference at virtual 
address 0000000000000000
[    0.724977] Mem abort info:                                                                                                       
[    0.727775]   ESR = 0x96000004                                                                                                    
[    0.730835]   EC = 0x25: DABT (current EL), IL = 32 bits                                                                          
[    0.736177]   SET = 0, FnV = 0                                                                                                    
[    0.739239]   EA = 0, S1PTW = 0                                                                                                   
[    0.742382]   FSC = 0x04: level 0 translation fault                                                                               
[    0.747287] Data abort info:                                                                                                      
[    0.750172]   ISV = 0, ISS = 0x00000004                                                                                           
[    0.754027]   CM = 0, WnR = 0                                                                                                     
[    0.757002] [0000000000000000] user address but active_mm is swapper                                                              
[    0.763394] Internal error: Oops: 96000004 [#1] PREEMPT SMP                                                                       
[    0.768985] Modules linked in:                                                                                                    
[    0.772049] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.17.0-next-20220331+ 
#48 8e9d24095c7f6b15f85bc2ad57a5609e219130b9          
[    0.782984] Hardware name: TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL (DT)                                                       
[    0.789985] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)                                                       
[    0.796985] pc : clk_mux_determine_rate_flags+0x280/0x2cc                                                                         
[    0.802407] lr : clk_mux_determine_rate_flags+0xf4/0x2cc                                                                          
[    0.807747] sp : ffff800009ceb590                                                                                                 
[    0.811072] x29: ffff800009ceb590 x28: ffff800009ceb6a0 x27: 
ffff800008eaa038                                                     
[    0.818245] x26: ffff8000092fe0b0 x25: ffff000000090000 x24: 
ffff000000090000                                                     
[    0.825420] x23: 0000000000000000 x22: ffff800008ea95d8 x21: 
ffff0000028f4700                                                     
[    0.832595] x20: 000000002faf0800 x19: 0000000000000000 x18: 
0000000000004590                                                     
[    0.839770] x17: 0000000000004570 x16: 0000000000004560 x15: 
ffff8000092ff250                                                     
[    0.846945] x14: 0000000000000000 x13: 3030303030303030 x12: 
3820657461722074                                                     
[    0.854120] x11: 6e6572617020746e x10: 6572727563203a73 x9 : 
7563203a7367616c                                                     
[    0.861295] x8 : 665f657461725f65 x7 : 205d373834393037 x6 : 
ffff800009a947c8                                                     
[    0.868472] x5 : ffff800008eafe68 x4 : 0000000000000009 x3 : 
000000002faf0800                                                     
[    0.875645] x2 : ffff800008eafef4 x1 : ffff800008eaa038 x0 : 
ffff8000092fd5b8                                                     
[    0.882822] Call trace:                                                                                                           
[    0.885273]  clk_mux_determine_rate_flags+0x280/0x2cc                                                                             
[    0.890347]  clk_mux_determine_rate+0x10/0x20                                                                                     
[    0.894720]  clk_core_determine_round_nolock+0x4c/0xb4                                                                            
[    0.899882]  clk_core_round_rate_nolock+0x30/0x80                                                                                 
[    0.904607]  clk_core_round_rate_nolock+0x70/0x80                                                                                 
[    0.909334]  clk_hw_round_rate+0x44/0x74                                                                                          
[    0.913270]  clk_factor_round_rate+0x60/0x80                                                                                      
[    0.917557]  clk_core_determine_round_nolock+0x88/0xb4                                                                            
[    0.922720]  clk_core_round_rate_nolock+0x30/0x80                                                                                 
[    0.927445]  clk_core_set_rate_nolock.part.0+0xa4/0x1d0                                                                           
[    0.932695]  clk_set_rate_range_nolock+0x234/0x244                                                                                
[    0.937507]  __clk_put+0x60/0x12c                                                                                                 
[    0.940834]  clk_put+0xc/0x1c                                                                                                     
[    0.943809]  __set_clk_parents+0x12c/0x244                                                                                        
[    0.947920]  of_clk_set_defaults+0x20/0x50                                                                                        
[    0.952032]  of_clk_add_hw_provider.part.0+0x94/0x120                                                                             
[    0.957107]  of_clk_add_hw_provider+0x10/0x20                                                                                     
[    0.961482]  imx8mp_clocks_probe+0x3458/0x34d0                                                                                    
[    0.965945]  platform_probe+0x64/0x100                                                                                            
[    0.969707]  call_driver_probe+0x28/0x130                                                                                         
[    0.973732]  really_probe+0x178/0x310                                                                                             
[    0.977409]  __driver_probe_device+0xfc/0x144                                                                                     
[    0.981782]  driver_probe_device+0x38/0x12c                                                                                       
[    0.985982]  __driver_attach+0xcc/0x220                                                                                           
[    0.989834]  bus_for_each_dev+0x6c/0xc0                                                                                           
[    0.993682]  driver_attach+0x20/0x2c                                                                                              
[    0.997270]  bus_add_driver+0x140/0x230                                                                                           
[    1.001120]  driver_register+0x74/0x120                                                                                           
[    1.004970]  __platform_driver_register+0x24/0x30                                                                                 
[    1.009697]  imx8mp_clk_driver_init+0x18/0x20                                                                                     
[    1.014070]  do_one_initcall+0x58/0x200                                                                                           
[    1.017920]  do_initcalls+0x164/0x19c                                                                                             
[    1.021597]  kernel_init_freeable+0x134/0x17c                                                                                     
[    1.025970]  kernel_init+0x2c/0x150                                                                                               
[    1.029470]  ret_from_fork+0x10/0x20                                                                                              
[    1.033065] Code: f9000f94 912982c1 b0002900 9116e000 (f9400262)                                                                  
[    1.039188] ---[ end trace 0000000000000000 ]---                                                                                  
[    1.043869] Kernel panic - not syncing: Attempted to kill init! 
exitcode=0x0000000b                                               
[    1.051523] SMP: stopping secondary CPUs                                                                                          
[    1.055467] Kernel Offset: disabled                                                                                               
[    1.058960] CPU features: 0x000,00020009,00001082                                                                                 
[    1.063684] Memory Limit: none                                                                                                    
[    1.066748] ---[ end Kernel panic - not syncing: Attempted to kill init! 
exitcode=0x0000000b ]---
---

With the $subject patch reverted and bootable system:
---
[    0.659922] clk_core_set_rate_nolock: rate 1000000000                                                                             
[    0.662154] clk_core_set_rate_nolock: rounded rate 1000000000                                                                     
[    0.667932] clk_core_set_rate_nolock: rate 800000000                                                                              
[    0.672918] clk_core_set_rate_nolock: rounded rate 800000000                                                                      
[    0.678601] clk_core_set_rate_nolock: rate 500000000                                                                              
[    0.683592] clk_core_set_rate_nolock: rounded rate 500000000                                                                      
[    0.689276] clk_core_set_rate_nolock: rate 400000000                                                                              
[    0.694267] clk_core_set_rate_nolock: rounded rate 400000000                                                                      
[    0.699980] clk_core_set_rate_nolock: rate 800000000                                                                              
[    0.704942] clk_core_set_rate_nolock: rounded rate 800000000                                                                      
[    0.710627] clk_core_set_rate_nolock: rate 393216000                                                                              
[    0.715611] clk_core_set_rate_nolock: rounded rate 393216000                                                                      
[    0.721815] clk_core_set_rate_nolock: rate 361267200                                                                              
[    0.726284] clk_core_set_rate_nolock: rounded rate 361267200                                                                      
[    0.734097] clk_core_set_rate_nolock: rate 800000000                                                                              
[    0.736977] clk_core_set_rate_nolock: rounded rate 800000000                                                                      
[    0.742652] clk_core_set_rate_nolock: rate 400000000                                                                              
[    0.747645] clk_core_set_rate_nolock: rounded rate 400000000                                                                      
[    0.754565] clk_core_set_rate_nolock: rate 500000000                                                                              
[    0.758331] clk_core_set_rate_nolock: rounded rate 500000000                                                                      
[    0.764688] SoC: i.MX8MP revision 1.1                                                                                             
[    0.767931] clk_core_set_rate_nolock: rate 500000000                                                                              
[    0.772675] clk_core_set_rate_nolock: rounded rate 500000000                                                                      
[    0.778354] clk_core_set_rate_nolock: rate 200000000                                                                              
[    0.783351] clk_core_set_rate_nolock: rounded rate 200000000                                                                      
[    0.793748] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled                                                               
[    0.798952] 30860000.serial: ttymxc0 at MMIO 0x30860000 (irq = 34, 
base_baud = 5000000) is a IMX                                  
[    0.806527] 30880000.serial: ttymxc2 at MMIO 0x30880000 (irq = 35, 
base_baud = 5000000) is a IMX                                  
[    0.815329] 30890000.serial: ttymxc1 at MMIO 0x30890000 (irq = 36, 
base_baud = 5000000) is a IMX                                  
[    0.824176] 30a60000.serial: ttymxc3 at MMIO 0x30a60000 (irq = 43, 
base_baud = 1500000) is a IMX                                  
[    0.832588] printk: console [ttymxc3] enabled                                                                                     
[    0.832588] printk: console [ttymxc3] enabled                                                                                     
[    0.841244] printk: bootconsole [ec_imx6q0] disabled                                                                              
[    0.841244] printk: bootconsole [ec_imx6q0] disabled                                                                              
[    0.857871] clk_core_set_rate_nolock: rate 80000000                                                                               
[    0.862796] clk_core_set_rate_nolock: rounded rate 80000000                                                                       
[    0.868469] clk_core_set_rate_nolock: rate 20000000                                                                               
[    0.873364] clk_core_set_rate_nolock: rounded rate 20000000                                                                       
[    0.879258] clk_core_set_rate_nolock: rate 80000000                                                                               
[    0.884154] clk_core_set_rate_nolock: rounded rate 80000000
[...]
---

The 500000000 and 800000000 look a bit like the assigned-clock-rates for 
clock-controller@30380000 in arch/arm64/boot/dts/freescale/imx8mp.dtsi

If you need some more information, do not hesitate to ask

Best regards,
Alexander

[1] https://lore.kernel.org/all/1911426.usQuhbGJ8B@steina-w/

Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 20054 bytes --]

Hi Alexander, Tony, Marek,

On Fri, Apr 01, 2022 at 01:55:20PM +0200, Alexander Stein wrote:
> Am Donnerstag, 31. März 2022, 17:31:34 CEST schrieb Maxime Ripard:
> > * PGP Signed by an unknown key
> > 
> > Hi Tony,
> > 
> > On Thu, Mar 31, 2022 at 06:00:42PM +0300, Tony Lindgren wrote:
> > > * Maxime Ripard <maxime@cerno.tech> [220331 09:52]:
> > > > On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> > > > > It seems the dts assigned-clock-parents no longer works now?
> > > > 
> > > > That would make some kind of sense, __set_clk_parents calls clk_put on
> > > > both the assigned clock and its parent.
> > > > 
> > > > Could you see what parent (and why?) it tries to enforce then?
> > > 
> > > It picks the other option available for the mux clock that only has
> > > two options. No idea why, but if you have some debug patch in mind I
> > > can give it a try.
> > > 
> > > > It looks like the gpt1_fck driver might favor another parent for that
> > > > rate, which, if it's an invalid configuration, shouldn't really happen?
> > > 
> > > Hmm there's a gate clock and a mux clock, there's not really a rate
> > > selection available here for the sources.
> > 
> > If I followed the OMAP driver properly, clk_mux_determine_rate_flags is
> > doing the heavy lifting, could you run your test with
> 
> I'm affected by this patch as well on an imx8mp platform (see [1] for some 
> details)
> 
> In the failing case with with your patch applied I get the following error 
> ---
> [    0.661064] clk_set_rate_range_nolock: core req rate 500000000                                                                    
> [    0.664084] clk_set_rate_range_nolock: clamped rate 500000000                                                                     
> [    0.669851] clk_core_set_rate_nolock: rate 500000000                                                                              
> [    0.674843] clk_core_set_rate_nolock: rounded rate 500000000                                                                      
> [    0.680536] clk_set_rate_range_nolock: core req rate 800000000                                                                    
> [    0.686389] clk_set_rate_range_nolock: clamped rate 800000000                                                                     
> [    0.692164] clk_core_set_rate_nolock: rate 800000000                                                                              
> [    0.697153] clk_mux_determine_rate_flags: requested rate 800000000                                                                
> [    0.703363] clk_mux_determine_rate_flags: current parent sys_pll1                                                                 
> [    0.709487] clk_mux_determine_rate_flags: current parent rate 800000000                                                           
> [    0.716147] Unable to handle kernel NULL pointer dereference at virtual 
> address 0000000000000000
> [    0.724977] Mem abort info:                                                                                                       
> [    0.727775]   ESR = 0x96000004                                                                                                    
> [    0.730835]   EC = 0x25: DABT (current EL), IL = 32 bits                                                                          
> [    0.736177]   SET = 0, FnV = 0                                                                                                    
> [    0.739239]   EA = 0, S1PTW = 0                                                                                                   
> [    0.742382]   FSC = 0x04: level 0 translation fault                                                                               
> [    0.747287] Data abort info:                                                                                                      
> [    0.750172]   ISV = 0, ISS = 0x00000004                                                                                           
> [    0.754027]   CM = 0, WnR = 0                                                                                                     
> [    0.757002] [0000000000000000] user address but active_mm is swapper                                                              
> [    0.763394] Internal error: Oops: 96000004 [#1] PREEMPT SMP                                                                       
> [    0.768985] Modules linked in:                                                                                                    
> [    0.772049] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.17.0-next-20220331+ 
> #48 8e9d24095c7f6b15f85bc2ad57a5609e219130b9          
> [    0.782984] Hardware name: TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL (DT)                                                       
> [    0.789985] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)                                                       
> [    0.796985] pc : clk_mux_determine_rate_flags+0x280/0x2cc                                                                         
> [    0.802407] lr : clk_mux_determine_rate_flags+0xf4/0x2cc                                                                          
> [    0.807747] sp : ffff800009ceb590                                                                                                 
> [    0.811072] x29: ffff800009ceb590 x28: ffff800009ceb6a0 x27: 
> ffff800008eaa038                                                     
> [    0.818245] x26: ffff8000092fe0b0 x25: ffff000000090000 x24: 
> ffff000000090000                                                     
> [    0.825420] x23: 0000000000000000 x22: ffff800008ea95d8 x21: 
> ffff0000028f4700                                                     
> [    0.832595] x20: 000000002faf0800 x19: 0000000000000000 x18: 
> 0000000000004590                                                     
> [    0.839770] x17: 0000000000004570 x16: 0000000000004560 x15: 
> ffff8000092ff250                                                     
> [    0.846945] x14: 0000000000000000 x13: 3030303030303030 x12: 
> 3820657461722074                                                     
> [    0.854120] x11: 6e6572617020746e x10: 6572727563203a73 x9 : 
> 7563203a7367616c                                                     
> [    0.861295] x8 : 665f657461725f65 x7 : 205d373834393037 x6 : 
> ffff800009a947c8                                                     
> [    0.868472] x5 : ffff800008eafe68 x4 : 0000000000000009 x3 : 
> 000000002faf0800                                                     
> [    0.875645] x2 : ffff800008eafef4 x1 : ffff800008eaa038 x0 : 
> ffff8000092fd5b8                                                     
> [    0.882822] Call trace:                                                                                                           
> [    0.885273]  clk_mux_determine_rate_flags+0x280/0x2cc                                                                             
> [    0.890347]  clk_mux_determine_rate+0x10/0x20                                                                                     
> [    0.894720]  clk_core_determine_round_nolock+0x4c/0xb4                                                                            
> [    0.899882]  clk_core_round_rate_nolock+0x30/0x80                                                                                 
> [    0.904607]  clk_core_round_rate_nolock+0x70/0x80                                                                                 
> [    0.909334]  clk_hw_round_rate+0x44/0x74                                                                                          
> [    0.913270]  clk_factor_round_rate+0x60/0x80                                                                                      
> [    0.917557]  clk_core_determine_round_nolock+0x88/0xb4                                                                            
> [    0.922720]  clk_core_round_rate_nolock+0x30/0x80                                                                                 
> [    0.927445]  clk_core_set_rate_nolock.part.0+0xa4/0x1d0                                                                           
> [    0.932695]  clk_set_rate_range_nolock+0x234/0x244                                                                                
> [    0.937507]  __clk_put+0x60/0x12c                                                                                                 
> [    0.940834]  clk_put+0xc/0x1c                                                                                                     
> [    0.943809]  __set_clk_parents+0x12c/0x244                                                                                        
> [    0.947920]  of_clk_set_defaults+0x20/0x50                                                                                        
> [    0.952032]  of_clk_add_hw_provider.part.0+0x94/0x120                                                                             
> [    0.957107]  of_clk_add_hw_provider+0x10/0x20                                                                                     
> [    0.961482]  imx8mp_clocks_probe+0x3458/0x34d0                                                                                    
> [    0.965945]  platform_probe+0x64/0x100                                                                                            
> [    0.969707]  call_driver_probe+0x28/0x130                                                                                         
> [    0.973732]  really_probe+0x178/0x310                                                                                             
> [    0.977409]  __driver_probe_device+0xfc/0x144                                                                                     
> [    0.981782]  driver_probe_device+0x38/0x12c                                                                                       
> [    0.985982]  __driver_attach+0xcc/0x220                                                                                           
> [    0.989834]  bus_for_each_dev+0x6c/0xc0                                                                                           
> [    0.993682]  driver_attach+0x20/0x2c                                                                                              
> [    0.997270]  bus_add_driver+0x140/0x230                                                                                           
> [    1.001120]  driver_register+0x74/0x120                                                                                           
> [    1.004970]  __platform_driver_register+0x24/0x30                                                                                 
> [    1.009697]  imx8mp_clk_driver_init+0x18/0x20                                                                                     
> [    1.014070]  do_one_initcall+0x58/0x200                                                                                           
> [    1.017920]  do_initcalls+0x164/0x19c                                                                                             
> [    1.021597]  kernel_init_freeable+0x134/0x17c                                                                                     
> [    1.025970]  kernel_init+0x2c/0x150                                                                                               
> [    1.029470]  ret_from_fork+0x10/0x20                                                                                              
> [    1.033065] Code: f9000f94 912982c1 b0002900 9116e000 (f9400262)                                                                  
> [    1.039188] ---[ end trace 0000000000000000 ]---                                                                                  
> [    1.043869] Kernel panic - not syncing: Attempted to kill init! 
> exitcode=0x0000000b                                               
> [    1.051523] SMP: stopping secondary CPUs                                                                                          
> [    1.055467] Kernel Offset: disabled                                                                                               
> [    1.058960] CPU features: 0x000,00020009,00001082                                                                                 
> [    1.063684] Memory Limit: none                                                                                                    
> [    1.066748] ---[ end Kernel panic - not syncing: Attempted to kill init! 
> exitcode=0x0000000b ]---
> ---
> 
> With the $subject patch reverted and bootable system:
> ---
> [    0.659922] clk_core_set_rate_nolock: rate 1000000000                                                                             
> [    0.662154] clk_core_set_rate_nolock: rounded rate 1000000000                                                                     
> [    0.667932] clk_core_set_rate_nolock: rate 800000000                                                                              
> [    0.672918] clk_core_set_rate_nolock: rounded rate 800000000                                                                      
> [    0.678601] clk_core_set_rate_nolock: rate 500000000                                                                              
> [    0.683592] clk_core_set_rate_nolock: rounded rate 500000000                                                                      
> [    0.689276] clk_core_set_rate_nolock: rate 400000000                                                                              
> [    0.694267] clk_core_set_rate_nolock: rounded rate 400000000                                                                      
> [    0.699980] clk_core_set_rate_nolock: rate 800000000                                                                              
> [    0.704942] clk_core_set_rate_nolock: rounded rate 800000000                                                                      
> [    0.710627] clk_core_set_rate_nolock: rate 393216000                                                                              
> [    0.715611] clk_core_set_rate_nolock: rounded rate 393216000                                                                      
> [    0.721815] clk_core_set_rate_nolock: rate 361267200                                                                              
> [    0.726284] clk_core_set_rate_nolock: rounded rate 361267200                                                                      
> [    0.734097] clk_core_set_rate_nolock: rate 800000000                                                                              
> [    0.736977] clk_core_set_rate_nolock: rounded rate 800000000                                                                      
> [    0.742652] clk_core_set_rate_nolock: rate 400000000                                                                              
> [    0.747645] clk_core_set_rate_nolock: rounded rate 400000000                                                                      
> [    0.754565] clk_core_set_rate_nolock: rate 500000000                                                                              
> [    0.758331] clk_core_set_rate_nolock: rounded rate 500000000                                                                      
> [    0.764688] SoC: i.MX8MP revision 1.1                                                                                             
> [    0.767931] clk_core_set_rate_nolock: rate 500000000                                                                              
> [    0.772675] clk_core_set_rate_nolock: rounded rate 500000000                                                                      
> [    0.778354] clk_core_set_rate_nolock: rate 200000000                                                                              
> [    0.783351] clk_core_set_rate_nolock: rounded rate 200000000                                                                      
> [    0.793748] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled                                                               
> [    0.798952] 30860000.serial: ttymxc0 at MMIO 0x30860000 (irq = 34, 
> base_baud = 5000000) is a IMX                                  
> [    0.806527] 30880000.serial: ttymxc2 at MMIO 0x30880000 (irq = 35, 
> base_baud = 5000000) is a IMX                                  
> [    0.815329] 30890000.serial: ttymxc1 at MMIO 0x30890000 (irq = 36, 
> base_baud = 5000000) is a IMX                                  
> [    0.824176] 30a60000.serial: ttymxc3 at MMIO 0x30a60000 (irq = 43, 
> base_baud = 1500000) is a IMX                                  
> [    0.832588] printk: console [ttymxc3] enabled                                                                                     
> [    0.832588] printk: console [ttymxc3] enabled                                                                                     
> [    0.841244] printk: bootconsole [ec_imx6q0] disabled                                                                              
> [    0.841244] printk: bootconsole [ec_imx6q0] disabled                                                                              
> [    0.857871] clk_core_set_rate_nolock: rate 80000000                                                                               
> [    0.862796] clk_core_set_rate_nolock: rounded rate 80000000                                                                       
> [    0.868469] clk_core_set_rate_nolock: rate 20000000                                                                               
> [    0.873364] clk_core_set_rate_nolock: rounded rate 20000000                                                                       
> [    0.879258] clk_core_set_rate_nolock: rate 80000000                                                                               
> [    0.884154] clk_core_set_rate_nolock: rounded rate 80000000
> [...]
> ---
> 
> The 500000000 and 800000000 look a bit like the assigned-clock-rates for 
> clock-controller@30380000 in arch/arm64/boot/dts/freescale/imx8mp.dtsi
> 
> If you need some more information, do not hesitate to ask

Thanks a lot to you three for all your testing. I think I know what
might be going on:

We use the last requested rate on clk_set_rate_range
(clk_core.req_rate), and that requested rate if the clock is orphan will
be set to 0, so if we were to call clk_set_rate_range before the parent
clock is registered, we would effectively call a clk_set_rate to 0

And the assigned-clocks stuff is handled by __set_clk_parents and
__set_clk_rates, called by of_clk_set_defaults(), in turn called by
of_clk_init and of_clk_add_provider. Both __set_clk_parents and
__set_clk_rates will call clk_put once done with the clock, and we will
with this patch trigger the clk_set_rate to 0 I mentioned before.

So we just became very good at triggering the underlying issue :)

And I think it's that while we update the requested rate when the
missing parent is registered, we never do when we mux away from it using
clk_set_parent.

Could you test the following patch and let me know if it works?

--->8---

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 91f863b7a824..ee5a0223e47d 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2599,6 +2599,8 @@ static int clk_core_set_parent_nolock(struct clk_core *core,
 	} else {
 		__clk_recalc_rates(core, POST_RATE_CHANGE);
 		__clk_recalc_accuracies(core);
+
+		core->req_rate = core->rate;
 	}

 runtime_put:

--->8---

Thanks!
Maxime

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: (EXT) Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Alexander Stein]

Hi Maxime,

Am Freitag, 1. April 2022, 14:27:36 CEST schrieb Maxime Ripard:
> On Fri, Apr 01, 2022 at 01:55:20PM +0200, Alexander Stein wrote:
> > Am Donnerstag, 31. März 2022, 17:31:34 CEST schrieb Maxime Ripard:
> > > > Old Signed by an unknown key
> > > 
> > > Hi Tony,
> > > 
> > > On Thu, Mar 31, 2022 at 06:00:42PM +0300, Tony Lindgren wrote:
> > > > * Maxime Ripard <maxime@cerno.tech> [220331 09:52]:
> > > > > On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> > > > > > It seems the dts assigned-clock-parents no longer works now?
> > > > > 
> > > > > That would make some kind of sense, __set_clk_parents calls clk_put
> > > > > on
> > > > > both the assigned clock and its parent.
> > > > > 
> > > > > Could you see what parent (and why?) it tries to enforce then?
> > > > 
> > > > It picks the other option available for the mux clock that only has
> > > > two options. No idea why, but if you have some debug patch in mind I
> > > > can give it a try.
> > > > 
> > > > > It looks like the gpt1_fck driver might favor another parent for
> > > > > that
> > > > > rate, which, if it's an invalid configuration, shouldn't really
> > > > > happen?
> > > > 
> > > > Hmm there's a gate clock and a mux clock, there's not really a rate
> > > > selection available here for the sources.
> > > 
> > > If I followed the OMAP driver properly, clk_mux_determine_rate_flags is
> > > doing the heavy lifting, could you run your test with
> > 
> > I'm affected by this patch as well on an imx8mp platform (see [1] for some
> > details)
> > 
> > In the failing case with with your patch applied I get the following error
> > ---
> > [    0.661064] clk_set_rate_range_nolock: core req rate 500000000
> > [    0.664084] clk_set_rate_range_nolock: clamped rate 500000000
> > [    0.669851] clk_core_set_rate_nolock: rate 500000000
> > [    0.674843] clk_core_set_rate_nolock: rounded rate 500000000
> > [    0.680536] clk_set_rate_range_nolock: core req rate 800000000
> > [    0.686389] clk_set_rate_range_nolock: clamped rate 800000000
> > [    0.692164] clk_core_set_rate_nolock: rate 800000000
> > [    0.697153] clk_mux_determine_rate_flags: requested rate 800000000
> > [    0.703363] clk_mux_determine_rate_flags: current parent sys_pll1
> > [    0.709487] clk_mux_determine_rate_flags: current parent rate 800000000
> > [    0.716147] Unable to handle kernel NULL pointer dereference at virtual
> > address 0000000000000000
> > [    0.724977] Mem abort info:
> > [    0.727775]   ESR = 0x96000004
> > [    0.730835]   EC = 0x25: DABT (current EL), IL = 32 bits
> > [    0.736177]   SET = 0, FnV = 0
> > [    0.739239]   EA = 0, S1PTW = 0
> > [    0.742382]   FSC = 0x04: level 0 translation fault
> > [    0.747287] Data abort info:
> > [    0.750172]   ISV = 0, ISS = 0x00000004
> > [    0.754027]   CM = 0, WnR = 0
> > [    0.757002] [0000000000000000] user address but active_mm is swapper
> > [    0.763394] Internal error: Oops: 96000004 [#1] PREEMPT SMP
> > [    0.768985] Modules linked in:
> > [    0.772049] CPU: 1 PID: 1 Comm: swapper/0 Not tainted
> > 5.17.0-next-20220331+ #48 8e9d24095c7f6b15f85bc2ad57a5609e219130b9
> > [    0.782984] Hardware name: TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL
> > (DT) [    0.789985] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS
> > BTYPE=--) [    0.796985] pc : clk_mux_determine_rate_flags+0x280/0x2cc
> > [    0.802407] lr : clk_mux_determine_rate_flags+0xf4/0x2cc
> > [    0.807747] sp : ffff800009ceb590
> > [    0.811072] x29: ffff800009ceb590 x28: ffff800009ceb6a0 x27:
> > ffff800008eaa038
> > [    0.818245] x26: ffff8000092fe0b0 x25: ffff000000090000 x24:
> > ffff000000090000
> > [    0.825420] x23: 0000000000000000 x22: ffff800008ea95d8 x21:
> > ffff0000028f4700
> > [    0.832595] x20: 000000002faf0800 x19: 0000000000000000 x18:
> > 0000000000004590
> > [    0.839770] x17: 0000000000004570 x16: 0000000000004560 x15:
> > ffff8000092ff250
> > [    0.846945] x14: 0000000000000000 x13: 3030303030303030 x12:
> > 3820657461722074
> > [    0.854120] x11: 6e6572617020746e x10: 6572727563203a73 x9 :
> > 7563203a7367616c
> > [    0.861295] x8 : 665f657461725f65 x7 : 205d373834393037 x6 :
> > ffff800009a947c8
> > [    0.868472] x5 : ffff800008eafe68 x4 : 0000000000000009 x3 :
> > 000000002faf0800
> > [    0.875645] x2 : ffff800008eafef4 x1 : ffff800008eaa038 x0 :
> > ffff8000092fd5b8
> > [    0.882822] Call trace:
> > [    0.885273]  clk_mux_determine_rate_flags+0x280/0x2cc
> > [    0.890347]  clk_mux_determine_rate+0x10/0x20
> > [    0.894720]  clk_core_determine_round_nolock+0x4c/0xb4
> > [    0.899882]  clk_core_round_rate_nolock+0x30/0x80
> > [    0.904607]  clk_core_round_rate_nolock+0x70/0x80
> > [    0.909334]  clk_hw_round_rate+0x44/0x74
> > [    0.913270]  clk_factor_round_rate+0x60/0x80
> > [    0.917557]  clk_core_determine_round_nolock+0x88/0xb4
> > [    0.922720]  clk_core_round_rate_nolock+0x30/0x80
> > [    0.927445]  clk_core_set_rate_nolock.part.0+0xa4/0x1d0
> > [    0.932695]  clk_set_rate_range_nolock+0x234/0x244
> > [    0.937507]  __clk_put+0x60/0x12c
> > [    0.940834]  clk_put+0xc/0x1c
> > [    0.943809]  __set_clk_parents+0x12c/0x244
> > [    0.947920]  of_clk_set_defaults+0x20/0x50
> > [    0.952032]  of_clk_add_hw_provider.part.0+0x94/0x120
> > [    0.957107]  of_clk_add_hw_provider+0x10/0x20
> > [    0.961482]  imx8mp_clocks_probe+0x3458/0x34d0
> > [    0.965945]  platform_probe+0x64/0x100
> > [    0.969707]  call_driver_probe+0x28/0x130
> > [    0.973732]  really_probe+0x178/0x310
> > [    0.977409]  __driver_probe_device+0xfc/0x144
> > [    0.981782]  driver_probe_device+0x38/0x12c
> > [    0.985982]  __driver_attach+0xcc/0x220
> > [    0.989834]  bus_for_each_dev+0x6c/0xc0
> > [    0.993682]  driver_attach+0x20/0x2c
> > [    0.997270]  bus_add_driver+0x140/0x230
> > [    1.001120]  driver_register+0x74/0x120
> > [    1.004970]  __platform_driver_register+0x24/0x30
> > [    1.009697]  imx8mp_clk_driver_init+0x18/0x20
> > [    1.014070]  do_one_initcall+0x58/0x200
> > [    1.017920]  do_initcalls+0x164/0x19c
> > [    1.021597]  kernel_init_freeable+0x134/0x17c
> > [    1.025970]  kernel_init+0x2c/0x150
> > [    1.029470]  ret_from_fork+0x10/0x20
> > [    1.033065] Code: f9000f94 912982c1 b0002900 9116e000 (f9400262)
> > [    1.039188] ---[ end trace 0000000000000000 ]---
> > [    1.043869] Kernel panic - not syncing: Attempted to kill init!
> > exitcode=0x0000000b
> > [    1.051523] SMP: stopping secondary CPUs
> > [    1.055467] Kernel Offset: disabled
> > [    1.058960] CPU features: 0x000,00020009,00001082
> > [    1.063684] Memory Limit: none
> > [    1.066748] ---[ end Kernel panic - not syncing: Attempted to kill
> > init!
> > exitcode=0x0000000b ]---
> > ---
> > 
> > With the $subject patch reverted and bootable system:
> > ---
> > [    0.659922] clk_core_set_rate_nolock: rate 1000000000
> > [    0.662154] clk_core_set_rate_nolock: rounded rate 1000000000
> > [    0.667932] clk_core_set_rate_nolock: rate 800000000
> > [    0.672918] clk_core_set_rate_nolock: rounded rate 800000000
> > [    0.678601] clk_core_set_rate_nolock: rate 500000000
> > [    0.683592] clk_core_set_rate_nolock: rounded rate 500000000
> > [    0.689276] clk_core_set_rate_nolock: rate 400000000
> > [    0.694267] clk_core_set_rate_nolock: rounded rate 400000000
> > [    0.699980] clk_core_set_rate_nolock: rate 800000000
> > [    0.704942] clk_core_set_rate_nolock: rounded rate 800000000
> > [    0.710627] clk_core_set_rate_nolock: rate 393216000
> > [    0.715611] clk_core_set_rate_nolock: rounded rate 393216000
> > [    0.721815] clk_core_set_rate_nolock: rate 361267200
> > [    0.726284] clk_core_set_rate_nolock: rounded rate 361267200
> > [    0.734097] clk_core_set_rate_nolock: rate 800000000
> > [    0.736977] clk_core_set_rate_nolock: rounded rate 800000000
> > [    0.742652] clk_core_set_rate_nolock: rate 400000000
> > [    0.747645] clk_core_set_rate_nolock: rounded rate 400000000
> > [    0.754565] clk_core_set_rate_nolock: rate 500000000
> > [    0.758331] clk_core_set_rate_nolock: rounded rate 500000000
> > [    0.764688] SoC: i.MX8MP revision 1.1
> > [    0.767931] clk_core_set_rate_nolock: rate 500000000
> > [    0.772675] clk_core_set_rate_nolock: rounded rate 500000000
> > [    0.778354] clk_core_set_rate_nolock: rate 200000000
> > [    0.783351] clk_core_set_rate_nolock: rounded rate 200000000
> > [    0.793748] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
> > [    0.798952] 30860000.serial: ttymxc0 at MMIO 0x30860000 (irq = 34,
> > base_baud = 5000000) is a IMX
> > [    0.806527] 30880000.serial: ttymxc2 at MMIO 0x30880000 (irq = 35,
> > base_baud = 5000000) is a IMX
> > [    0.815329] 30890000.serial: ttymxc1 at MMIO 0x30890000 (irq = 36,
> > base_baud = 5000000) is a IMX
> > [    0.824176] 30a60000.serial: ttymxc3 at MMIO 0x30a60000 (irq = 43,
> > base_baud = 1500000) is a IMX
> > [    0.832588] printk: console [ttymxc3] enabled
> > [    0.832588] printk: console [ttymxc3] enabled
> > [    0.841244] printk: bootconsole [ec_imx6q0] disabled
> > [    0.841244] printk: bootconsole [ec_imx6q0] disabled
> > [    0.857871] clk_core_set_rate_nolock: rate 80000000
> > [    0.862796] clk_core_set_rate_nolock: rounded rate 80000000
> > [    0.868469] clk_core_set_rate_nolock: rate 20000000
> > [    0.873364] clk_core_set_rate_nolock: rounded rate 20000000
> > [    0.879258] clk_core_set_rate_nolock: rate 80000000
> > [    0.884154] clk_core_set_rate_nolock: rounded rate 80000000
> > [...]
> > ---
> > 
> > The 500000000 and 800000000 look a bit like the assigned-clock-rates for
> > clock-controller@30380000 in arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > 
> > If you need some more information, do not hesitate to ask
> 
> Thanks a lot to you three for all your testing. I think I know what
> might be going on:
> 
> We use the last requested rate on clk_set_rate_range
> (clk_core.req_rate), and that requested rate if the clock is orphan will
> be set to 0, so if we were to call clk_set_rate_range before the parent
> clock is registered, we would effectively call a clk_set_rate to 0
> 
> And the assigned-clocks stuff is handled by __set_clk_parents and
> __set_clk_rates, called by of_clk_set_defaults(), in turn called by
> of_clk_init and of_clk_add_provider. Both __set_clk_parents and
> __set_clk_rates will call clk_put once done with the clock, and we will
> with this patch trigger the clk_set_rate to 0 I mentioned before.
> 
> So we just became very good at triggering the underlying issue :)
> 
> And I think it's that while we update the requested rate when the
> missing parent is registered, we never do when we mux away from it using
> clk_set_parent.
> 
> Could you test the following patch and let me know if it works?
> 
> --->8---
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 91f863b7a824..ee5a0223e47d 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -2599,6 +2599,8 @@ static int clk_core_set_parent_nolock(struct clk_core
> *core, } else {
>  		__clk_recalc_rates(core, POST_RATE_CHANGE);
>  		__clk_recalc_accuracies(core);
> +
> +		core->req_rate = core->rate;
>  	}
> 
>  runtime_put:
> 
> --->8---

Thanks for the patch. Unfortunately it does not help in my case. Here is the 
output form the other patch. It's the same clock (sys_pll1) but a different 
rate for the first calls.

---
[    0.658706] clk_set_rate_range_nolock: core req rate 800000000                                                                    
[    0.661715] clk_set_rate_range_nolock: clamped rate 800000000                                                                     
[    0.667496] clk_core_set_rate_nolock: rate 800000000                                                                              
[    0.672485] clk_core_set_rate_nolock: rounded rate 800000000                                                                      
[    0.678171] clk_set_rate_range_nolock: core req rate 800000000                                                                    
[    0.684033] clk_set_rate_range_nolock: clamped rate 800000000                                                                     
[    0.689804] clk_core_set_rate_nolock: rate 800000000                                                                              
[    0.694795] clk_mux_determine_rate_flags: requested rate 800000000                                                                
[    0.701005] clk_mux_determine_rate_flags: current parent sys_pll1                                                                 
[    0.707130] clk_mux_determine_rate_flags: current parent rate 800000000                                                           
[    0.713789] Unable to handle kernel NULL pointer dereference at virtual 
address 0000000000000000                                  
[    0.722618] Mem abort info:                                                                                                       
[    0.725411]   ESR = 0x96000004                                                                                                    
[    0.728483]   EC = 0x25: DABT (current EL), IL = 32 bits                                                                          
[    0.733822]   SET = 0, FnV = 0                                                                                                    
[    0.736879]   EA = 0, S1PTW = 0                                                                                                   
[    0.740032]   FSC = 0x04: level 0 translation fault
[    0.744930] Data abort info:
[    0.747820]   ISV = 0, ISS = 0x00000004
[    0.751666]   CM = 0, WnR = 0
[    0.754645] [0000000000000000] user address but active_mm is swapper
[    0.761034] Internal error: Oops: 96000004 [#1] PREEMPT SMP
[    0.766627] Modules linked in:
[    0.769690] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.17.0-next-20220331+ 
#51 62b66a4e908a3493b6d37735830c8ba1462e0fc9
[    0.780625] Hardware name: TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL (DT)
[    0.787627] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[    0.794625] pc : clk_mux_determine_rate_flags+0x280/0x2cc
[    0.800049] lr : clk_mux_determine_rate_flags+0xf4/0x2cc
[    0.805388] sp : ffff800009ceb590
[    0.808713] x29: ffff800009ceb590 x28: ffff800009ceb6a0 x27: 
ffff800008eaa038
[    0.815886] x26: ffff8000092fe090 x25: ffff000000090000 x24: 
ffff000000090000
[    0.823061] x23: 0000000000000000 x22: ffff800008ea95d8 x21: 
ffff000002aab700
[    0.830236] x20: 000000002faf0800 x19: 0000000000000000 x18: 
0000000000004590
[    0.837411] x17: 0000000000004570 x16: 0000000000004560 x15: 
ffff8000092ff230
[    0.844586] x14: 0000000000000000 x13: 3030303030303030 x12: 
3820657461722074
[    0.851761] x11: 6e6572617020746e x10: 6572727563203a73 x9 : 
7563203a7367616c
[    0.858936] x8 : 665f657461725f65 x7 : 205d303331373037 x6 : 
ffff800009a947c8
[    0.866113] x5 : ffff800008eafe68 x4 : 0000000000000009 x3 : 
000000002faf0800
[    0.873286] x2 : ffff800008eafef4 x1 : ffff800008eaa038 x0 : 
ffff8000092fd598
[    0.880464] Call trace:
[    0.882914]  clk_mux_determine_rate_flags+0x280/0x2cc
[    0.887989]  clk_mux_determine_rate+0x10/0x20
[    0.892361]  clk_core_determine_round_nolock+0x4c/0xb4
[    0.897524]  clk_core_round_rate_nolock+0x30/0x80
[    0.902249]  clk_core_round_rate_nolock+0x70/0x80
[    0.906976]  clk_hw_round_rate+0x44/0x74
[    0.910911]  clk_factor_round_rate+0x60/0x80
[    0.915199]  clk_core_determine_round_nolock+0x88/0xb4
[    0.920361]  clk_core_round_rate_nolock+0x30/0x80
[    0.925086]  clk_core_set_rate_nolock.part.0+0xa4/0x1d0
[    0.930336]  clk_set_rate_range_nolock+0x234/0x244
[    0.935149]  __clk_put+0x60/0x12c
[    0.938474]  clk_put+0xc/0x1c
[    0.941451]  __set_clk_parents+0x12c/0x244
[    0.945561]  of_clk_set_defaults+0x20/0x50
[    0.949674]  of_clk_add_hw_provider.part.0+0x94/0x120
[    0.954750]  of_clk_add_hw_provider+0x10/0x20
[    0.959124]  imx8mp_clocks_probe+0x3458/0x34d0
[    0.963586]  platform_probe+0x64/0x100
[    0.967349]  call_driver_probe+0x28/0x130
[    0.971374]  really_probe+0x178/0x310
[    0.975051]  __driver_probe_device+0xfc/0x144
[    0.979424]  driver_probe_device+0x38/0x12c
[    0.983624]  __driver_attach+0xcc/0x220
[    0.987476]  bus_for_each_dev+0x6c/0xc0
[    0.991324]  driver_attach+0x20/0x2c
[    0.994911]  bus_add_driver+0x140/0x230
[    0.998761]  driver_register+0x74/0x120
[    1.002611]  __platform_driver_register+0x24/0x30
[    1.007338]  imx8mp_clk_driver_init+0x18/0x20
[    1.011711]  do_one_initcall+0x58/0x200
[    1.015561]  do_initcalls+0x164/0x19c
[    1.019238]  kernel_init_freeable+0x134/0x17c
[    1.023613]  kernel_init+0x2c/0x150
[    1.027111]  ret_from_fork+0x10/0x20
[    1.030705] Code: f9000f94 912982c1 d0002900 91166000 (f9400262) 
[    1.036829] ---[ end trace 0000000000000000 ]---
[    1.041512] Kernel panic - not syncing: Attempted to kill init! 
exitcode=0x0000000b
[    1.049164] SMP: stopping secondary CPUs
[    1.053108] Kernel Offset: disabled
[    1.056600] CPU features: 0x000,00020009,00001082
[    1.061326] Memory Limit: none
[    1.064390] ---[ end Kernel panic - not syncing: Attempted to kill init! 
exitcode=0x0000000b ]---

Best regards,
Alexander

Re: (EXT) Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 18442 bytes --]

On Fri, Apr 01, 2022 at 02:59:37PM +0200, Alexander Stein wrote:
> Hi Maxime,
> 
> Am Freitag, 1. April 2022, 14:27:36 CEST schrieb Maxime Ripard:
> > On Fri, Apr 01, 2022 at 01:55:20PM +0200, Alexander Stein wrote:
> > > Am Donnerstag, 31. März 2022, 17:31:34 CEST schrieb Maxime Ripard:
> > > > > Old Signed by an unknown key
> > > > 
> > > > Hi Tony,
> > > > 
> > > > On Thu, Mar 31, 2022 at 06:00:42PM +0300, Tony Lindgren wrote:
> > > > > * Maxime Ripard <maxime@cerno.tech> [220331 09:52]:
> > > > > > On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> > > > > > > It seems the dts assigned-clock-parents no longer works now?
> > > > > > 
> > > > > > That would make some kind of sense, __set_clk_parents calls clk_put
> > > > > > on
> > > > > > both the assigned clock and its parent.
> > > > > > 
> > > > > > Could you see what parent (and why?) it tries to enforce then?
> > > > > 
> > > > > It picks the other option available for the mux clock that only has
> > > > > two options. No idea why, but if you have some debug patch in mind I
> > > > > can give it a try.
> > > > > 
> > > > > > It looks like the gpt1_fck driver might favor another parent for
> > > > > > that
> > > > > > rate, which, if it's an invalid configuration, shouldn't really
> > > > > > happen?
> > > > > 
> > > > > Hmm there's a gate clock and a mux clock, there's not really a rate
> > > > > selection available here for the sources.
> > > > 
> > > > If I followed the OMAP driver properly, clk_mux_determine_rate_flags is
> > > > doing the heavy lifting, could you run your test with
> > > 
> > > I'm affected by this patch as well on an imx8mp platform (see [1] for some
> > > details)
> > > 
> > > In the failing case with with your patch applied I get the following error
> > > ---
> > > [    0.661064] clk_set_rate_range_nolock: core req rate 500000000
> > > [    0.664084] clk_set_rate_range_nolock: clamped rate 500000000
> > > [    0.669851] clk_core_set_rate_nolock: rate 500000000
> > > [    0.674843] clk_core_set_rate_nolock: rounded rate 500000000
> > > [    0.680536] clk_set_rate_range_nolock: core req rate 800000000
> > > [    0.686389] clk_set_rate_range_nolock: clamped rate 800000000
> > > [    0.692164] clk_core_set_rate_nolock: rate 800000000
> > > [    0.697153] clk_mux_determine_rate_flags: requested rate 800000000
> > > [    0.703363] clk_mux_determine_rate_flags: current parent sys_pll1
> > > [    0.709487] clk_mux_determine_rate_flags: current parent rate 800000000
> > > [    0.716147] Unable to handle kernel NULL pointer dereference at virtual
> > > address 0000000000000000
> > > [    0.724977] Mem abort info:
> > > [    0.727775]   ESR = 0x96000004
> > > [    0.730835]   EC = 0x25: DABT (current EL), IL = 32 bits
> > > [    0.736177]   SET = 0, FnV = 0
> > > [    0.739239]   EA = 0, S1PTW = 0
> > > [    0.742382]   FSC = 0x04: level 0 translation fault
> > > [    0.747287] Data abort info:
> > > [    0.750172]   ISV = 0, ISS = 0x00000004
> > > [    0.754027]   CM = 0, WnR = 0
> > > [    0.757002] [0000000000000000] user address but active_mm is swapper
> > > [    0.763394] Internal error: Oops: 96000004 [#1] PREEMPT SMP
> > > [    0.768985] Modules linked in:
> > > [    0.772049] CPU: 1 PID: 1 Comm: swapper/0 Not tainted
> > > 5.17.0-next-20220331+ #48 8e9d24095c7f6b15f85bc2ad57a5609e219130b9
> > > [    0.782984] Hardware name: TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL
> > > (DT) [    0.789985] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS
> > > BTYPE=--) [    0.796985] pc : clk_mux_determine_rate_flags+0x280/0x2cc
> > > [    0.802407] lr : clk_mux_determine_rate_flags+0xf4/0x2cc
> > > [    0.807747] sp : ffff800009ceb590
> > > [    0.811072] x29: ffff800009ceb590 x28: ffff800009ceb6a0 x27:
> > > ffff800008eaa038
> > > [    0.818245] x26: ffff8000092fe0b0 x25: ffff000000090000 x24:
> > > ffff000000090000
> > > [    0.825420] x23: 0000000000000000 x22: ffff800008ea95d8 x21:
> > > ffff0000028f4700
> > > [    0.832595] x20: 000000002faf0800 x19: 0000000000000000 x18:
> > > 0000000000004590
> > > [    0.839770] x17: 0000000000004570 x16: 0000000000004560 x15:
> > > ffff8000092ff250
> > > [    0.846945] x14: 0000000000000000 x13: 3030303030303030 x12:
> > > 3820657461722074
> > > [    0.854120] x11: 6e6572617020746e x10: 6572727563203a73 x9 :
> > > 7563203a7367616c
> > > [    0.861295] x8 : 665f657461725f65 x7 : 205d373834393037 x6 :
> > > ffff800009a947c8
> > > [    0.868472] x5 : ffff800008eafe68 x4 : 0000000000000009 x3 :
> > > 000000002faf0800
> > > [    0.875645] x2 : ffff800008eafef4 x1 : ffff800008eaa038 x0 :
> > > ffff8000092fd5b8
> > > [    0.882822] Call trace:
> > > [    0.885273]  clk_mux_determine_rate_flags+0x280/0x2cc
> > > [    0.890347]  clk_mux_determine_rate+0x10/0x20
> > > [    0.894720]  clk_core_determine_round_nolock+0x4c/0xb4
> > > [    0.899882]  clk_core_round_rate_nolock+0x30/0x80
> > > [    0.904607]  clk_core_round_rate_nolock+0x70/0x80
> > > [    0.909334]  clk_hw_round_rate+0x44/0x74
> > > [    0.913270]  clk_factor_round_rate+0x60/0x80
> > > [    0.917557]  clk_core_determine_round_nolock+0x88/0xb4
> > > [    0.922720]  clk_core_round_rate_nolock+0x30/0x80
> > > [    0.927445]  clk_core_set_rate_nolock.part.0+0xa4/0x1d0
> > > [    0.932695]  clk_set_rate_range_nolock+0x234/0x244
> > > [    0.937507]  __clk_put+0x60/0x12c
> > > [    0.940834]  clk_put+0xc/0x1c
> > > [    0.943809]  __set_clk_parents+0x12c/0x244
> > > [    0.947920]  of_clk_set_defaults+0x20/0x50
> > > [    0.952032]  of_clk_add_hw_provider.part.0+0x94/0x120
> > > [    0.957107]  of_clk_add_hw_provider+0x10/0x20
> > > [    0.961482]  imx8mp_clocks_probe+0x3458/0x34d0
> > > [    0.965945]  platform_probe+0x64/0x100
> > > [    0.969707]  call_driver_probe+0x28/0x130
> > > [    0.973732]  really_probe+0x178/0x310
> > > [    0.977409]  __driver_probe_device+0xfc/0x144
> > > [    0.981782]  driver_probe_device+0x38/0x12c
> > > [    0.985982]  __driver_attach+0xcc/0x220
> > > [    0.989834]  bus_for_each_dev+0x6c/0xc0
> > > [    0.993682]  driver_attach+0x20/0x2c
> > > [    0.997270]  bus_add_driver+0x140/0x230
> > > [    1.001120]  driver_register+0x74/0x120
> > > [    1.004970]  __platform_driver_register+0x24/0x30
> > > [    1.009697]  imx8mp_clk_driver_init+0x18/0x20
> > > [    1.014070]  do_one_initcall+0x58/0x200
> > > [    1.017920]  do_initcalls+0x164/0x19c
> > > [    1.021597]  kernel_init_freeable+0x134/0x17c
> > > [    1.025970]  kernel_init+0x2c/0x150
> > > [    1.029470]  ret_from_fork+0x10/0x20
> > > [    1.033065] Code: f9000f94 912982c1 b0002900 9116e000 (f9400262)
> > > [    1.039188] ---[ end trace 0000000000000000 ]---
> > > [    1.043869] Kernel panic - not syncing: Attempted to kill init!
> > > exitcode=0x0000000b
> > > [    1.051523] SMP: stopping secondary CPUs
> > > [    1.055467] Kernel Offset: disabled
> > > [    1.058960] CPU features: 0x000,00020009,00001082
> > > [    1.063684] Memory Limit: none
> > > [    1.066748] ---[ end Kernel panic - not syncing: Attempted to kill
> > > init!
> > > exitcode=0x0000000b ]---
> > > ---
> > > 
> > > With the $subject patch reverted and bootable system:
> > > ---
> > > [    0.659922] clk_core_set_rate_nolock: rate 1000000000
> > > [    0.662154] clk_core_set_rate_nolock: rounded rate 1000000000
> > > [    0.667932] clk_core_set_rate_nolock: rate 800000000
> > > [    0.672918] clk_core_set_rate_nolock: rounded rate 800000000
> > > [    0.678601] clk_core_set_rate_nolock: rate 500000000
> > > [    0.683592] clk_core_set_rate_nolock: rounded rate 500000000
> > > [    0.689276] clk_core_set_rate_nolock: rate 400000000
> > > [    0.694267] clk_core_set_rate_nolock: rounded rate 400000000
> > > [    0.699980] clk_core_set_rate_nolock: rate 800000000
> > > [    0.704942] clk_core_set_rate_nolock: rounded rate 800000000
> > > [    0.710627] clk_core_set_rate_nolock: rate 393216000
> > > [    0.715611] clk_core_set_rate_nolock: rounded rate 393216000
> > > [    0.721815] clk_core_set_rate_nolock: rate 361267200
> > > [    0.726284] clk_core_set_rate_nolock: rounded rate 361267200
> > > [    0.734097] clk_core_set_rate_nolock: rate 800000000
> > > [    0.736977] clk_core_set_rate_nolock: rounded rate 800000000
> > > [    0.742652] clk_core_set_rate_nolock: rate 400000000
> > > [    0.747645] clk_core_set_rate_nolock: rounded rate 400000000
> > > [    0.754565] clk_core_set_rate_nolock: rate 500000000
> > > [    0.758331] clk_core_set_rate_nolock: rounded rate 500000000
> > > [    0.764688] SoC: i.MX8MP revision 1.1
> > > [    0.767931] clk_core_set_rate_nolock: rate 500000000
> > > [    0.772675] clk_core_set_rate_nolock: rounded rate 500000000
> > > [    0.778354] clk_core_set_rate_nolock: rate 200000000
> > > [    0.783351] clk_core_set_rate_nolock: rounded rate 200000000
> > > [    0.793748] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
> > > [    0.798952] 30860000.serial: ttymxc0 at MMIO 0x30860000 (irq = 34,
> > > base_baud = 5000000) is a IMX
> > > [    0.806527] 30880000.serial: ttymxc2 at MMIO 0x30880000 (irq = 35,
> > > base_baud = 5000000) is a IMX
> > > [    0.815329] 30890000.serial: ttymxc1 at MMIO 0x30890000 (irq = 36,
> > > base_baud = 5000000) is a IMX
> > > [    0.824176] 30a60000.serial: ttymxc3 at MMIO 0x30a60000 (irq = 43,
> > > base_baud = 1500000) is a IMX
> > > [    0.832588] printk: console [ttymxc3] enabled
> > > [    0.832588] printk: console [ttymxc3] enabled
> > > [    0.841244] printk: bootconsole [ec_imx6q0] disabled
> > > [    0.841244] printk: bootconsole [ec_imx6q0] disabled
> > > [    0.857871] clk_core_set_rate_nolock: rate 80000000
> > > [    0.862796] clk_core_set_rate_nolock: rounded rate 80000000
> > > [    0.868469] clk_core_set_rate_nolock: rate 20000000
> > > [    0.873364] clk_core_set_rate_nolock: rounded rate 20000000
> > > [    0.879258] clk_core_set_rate_nolock: rate 80000000
> > > [    0.884154] clk_core_set_rate_nolock: rounded rate 80000000
> > > [...]
> > > ---
> > > 
> > > The 500000000 and 800000000 look a bit like the assigned-clock-rates for
> > > clock-controller@30380000 in arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > 
> > > If you need some more information, do not hesitate to ask
> > 
> > Thanks a lot to you three for all your testing. I think I know what
> > might be going on:
> > 
> > We use the last requested rate on clk_set_rate_range
> > (clk_core.req_rate), and that requested rate if the clock is orphan will
> > be set to 0, so if we were to call clk_set_rate_range before the parent
> > clock is registered, we would effectively call a clk_set_rate to 0
> > 
> > And the assigned-clocks stuff is handled by __set_clk_parents and
> > __set_clk_rates, called by of_clk_set_defaults(), in turn called by
> > of_clk_init and of_clk_add_provider. Both __set_clk_parents and
> > __set_clk_rates will call clk_put once done with the clock, and we will
> > with this patch trigger the clk_set_rate to 0 I mentioned before.
> > 
> > So we just became very good at triggering the underlying issue :)
> > 
> > And I think it's that while we update the requested rate when the
> > missing parent is registered, we never do when we mux away from it using
> > clk_set_parent.
> > 
> > Could you test the following patch and let me know if it works?
> > 
> > --->8---
> > 
> > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > index 91f863b7a824..ee5a0223e47d 100644
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -2599,6 +2599,8 @@ static int clk_core_set_parent_nolock(struct clk_core
> > *core, } else {
> >  		__clk_recalc_rates(core, POST_RATE_CHANGE);
> >  		__clk_recalc_accuracies(core);
> > +
> > +		core->req_rate = core->rate;
> >  	}
> > 
> >  runtime_put:
> > 
> > --->8---
> 
> Thanks for the patch. Unfortunately it does not help in my case. Here is the 
> output form the other patch. It's the same clock (sys_pll1) but a different 
> rate for the first calls.
> 
> ---
> [    0.658706] clk_set_rate_range_nolock: core req rate 800000000                                                                    
> [    0.661715] clk_set_rate_range_nolock: clamped rate 800000000                                                                     
> [    0.667496] clk_core_set_rate_nolock: rate 800000000                                                                              
> [    0.672485] clk_core_set_rate_nolock: rounded rate 800000000                                                                      
> [    0.678171] clk_set_rate_range_nolock: core req rate 800000000                                                                    
> [    0.684033] clk_set_rate_range_nolock: clamped rate 800000000                                                                     
> [    0.689804] clk_core_set_rate_nolock: rate 800000000                                                                              
> [    0.694795] clk_mux_determine_rate_flags: requested rate 800000000                                                                
> [    0.701005] clk_mux_determine_rate_flags: current parent sys_pll1                                                                 
> [    0.707130] clk_mux_determine_rate_flags: current parent rate 800000000                                                           
> [    0.713789] Unable to handle kernel NULL pointer dereference at virtual 
> address 0000000000000000                                  
> [    0.722618] Mem abort info:                                                                                                       
> [    0.725411]   ESR = 0x96000004                                                                                                    
> [    0.728483]   EC = 0x25: DABT (current EL), IL = 32 bits                                                                          
> [    0.733822]   SET = 0, FnV = 0                                                                                                    
> [    0.736879]   EA = 0, S1PTW = 0                                                                                                   
> [    0.740032]   FSC = 0x04: level 0 translation fault
> [    0.744930] Data abort info:
> [    0.747820]   ISV = 0, ISS = 0x00000004
> [    0.751666]   CM = 0, WnR = 0
> [    0.754645] [0000000000000000] user address but active_mm is swapper
> [    0.761034] Internal error: Oops: 96000004 [#1] PREEMPT SMP
> [    0.766627] Modules linked in:
> [    0.769690] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.17.0-next-20220331+ 
> #51 62b66a4e908a3493b6d37735830c8ba1462e0fc9
> [    0.780625] Hardware name: TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL (DT)
> [    0.787627] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [    0.794625] pc : clk_mux_determine_rate_flags+0x280/0x2cc
> [    0.800049] lr : clk_mux_determine_rate_flags+0xf4/0x2cc
> [    0.805388] sp : ffff800009ceb590
> [    0.808713] x29: ffff800009ceb590 x28: ffff800009ceb6a0 x27: 
> ffff800008eaa038
> [    0.815886] x26: ffff8000092fe090 x25: ffff000000090000 x24: 
> ffff000000090000
> [    0.823061] x23: 0000000000000000 x22: ffff800008ea95d8 x21: 
> ffff000002aab700
> [    0.830236] x20: 000000002faf0800 x19: 0000000000000000 x18: 
> 0000000000004590
> [    0.837411] x17: 0000000000004570 x16: 0000000000004560 x15: 
> ffff8000092ff230
> [    0.844586] x14: 0000000000000000 x13: 3030303030303030 x12: 
> 3820657461722074
> [    0.851761] x11: 6e6572617020746e x10: 6572727563203a73 x9 : 
> 7563203a7367616c
> [    0.858936] x8 : 665f657461725f65 x7 : 205d303331373037 x6 : 
> ffff800009a947c8
> [    0.866113] x5 : ffff800008eafe68 x4 : 0000000000000009 x3 : 
> 000000002faf0800
> [    0.873286] x2 : ffff800008eafef4 x1 : ffff800008eaa038 x0 : 
> ffff8000092fd598
> [    0.880464] Call trace:
> [    0.882914]  clk_mux_determine_rate_flags+0x280/0x2cc
> [    0.887989]  clk_mux_determine_rate+0x10/0x20
> [    0.892361]  clk_core_determine_round_nolock+0x4c/0xb4
> [    0.897524]  clk_core_round_rate_nolock+0x30/0x80
> [    0.902249]  clk_core_round_rate_nolock+0x70/0x80
> [    0.906976]  clk_hw_round_rate+0x44/0x74
> [    0.910911]  clk_factor_round_rate+0x60/0x80
> [    0.915199]  clk_core_determine_round_nolock+0x88/0xb4
> [    0.920361]  clk_core_round_rate_nolock+0x30/0x80
> [    0.925086]  clk_core_set_rate_nolock.part.0+0xa4/0x1d0
> [    0.930336]  clk_set_rate_range_nolock+0x234/0x244
> [    0.935149]  __clk_put+0x60/0x12c
> [    0.938474]  clk_put+0xc/0x1c
> [    0.941451]  __set_clk_parents+0x12c/0x244
> [    0.945561]  of_clk_set_defaults+0x20/0x50
> [    0.949674]  of_clk_add_hw_provider.part.0+0x94/0x120
> [    0.954750]  of_clk_add_hw_provider+0x10/0x20
> [    0.959124]  imx8mp_clocks_probe+0x3458/0x34d0
> [    0.963586]  platform_probe+0x64/0x100
> [    0.967349]  call_driver_probe+0x28/0x130
> [    0.971374]  really_probe+0x178/0x310
> [    0.975051]  __driver_probe_device+0xfc/0x144
> [    0.979424]  driver_probe_device+0x38/0x12c
> [    0.983624]  __driver_attach+0xcc/0x220
> [    0.987476]  bus_for_each_dev+0x6c/0xc0
> [    0.991324]  driver_attach+0x20/0x2c
> [    0.994911]  bus_add_driver+0x140/0x230
> [    0.998761]  driver_register+0x74/0x120
> [    1.002611]  __platform_driver_register+0x24/0x30
> [    1.007338]  imx8mp_clk_driver_init+0x18/0x20
> [    1.011711]  do_one_initcall+0x58/0x200
> [    1.015561]  do_initcalls+0x164/0x19c
> [    1.019238]  kernel_init_freeable+0x134/0x17c
> [    1.023613]  kernel_init+0x2c/0x150
> [    1.027111]  ret_from_fork+0x10/0x20
> [    1.030705] Code: f9000f94 912982c1 d0002900 91166000 (f9400262) 
> [    1.036829] ---[ end trace 0000000000000000 ]---
> [    1.041512] Kernel panic - not syncing: Attempted to kill init! 
> exitcode=0x0000000b
> [    1.049164] SMP: stopping secondary CPUs
> [    1.053108] Kernel Offset: disabled
> [    1.056600] CPU features: 0x000,00020009,00001082
> [    1.061326] Memory Limit: none
> [    1.064390] ---[ end Kernel panic - not syncing: Attempted to kill init! 
> exitcode=0x0000000b ]---

Does it also happen if you only apply the patch I had above, and not all
the debugging?

Maxime

[-- Attachment #2: signature.asc --]
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Re: (EXT) Re: (EXT) Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Alexander Stein]

Am Freitag, 1. April 2022, 15:04:42 CEST schrieb Maxime Ripard:
> * PGP Signed by an unknown key
> 
> On Fri, Apr 01, 2022 at 02:59:37PM +0200, Alexander Stein wrote:
> > Hi Maxime,
> > 
> > Am Freitag, 1. April 2022, 14:27:36 CEST schrieb Maxime Ripard:
> > > On Fri, Apr 01, 2022 at 01:55:20PM +0200, Alexander Stein wrote:
> > > > Am Donnerstag, 31. März 2022, 17:31:34 CEST schrieb Maxime Ripard:
> > > > > > Old Signed by an unknown key
> > > > > 
> > > > > Hi Tony,
> > > > > 
> > > > > On Thu, Mar 31, 2022 at 06:00:42PM +0300, Tony Lindgren wrote:
> > > > > > * Maxime Ripard <maxime@cerno.tech> [220331 09:52]:
> > > > > > > On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> > > > > > > > It seems the dts assigned-clock-parents no longer works now?
> > > > > > > 
> > > > > > > That would make some kind of sense, __set_clk_parents calls
> > > > > > > clk_put
> > > > > > > on
> > > > > > > both the assigned clock and its parent.
> > > > > > > 
> > > > > > > Could you see what parent (and why?) it tries to enforce then?
> > > > > > 
> > > > > > It picks the other option available for the mux clock that only
> > > > > > has
> > > > > > two options. No idea why, but if you have some debug patch in mind
> > > > > > I
> > > > > > can give it a try.
> > > > > > 
> > > > > > > It looks like the gpt1_fck driver might favor another parent for
> > > > > > > that
> > > > > > > rate, which, if it's an invalid configuration, shouldn't really
> > > > > > > happen?
> > > > > > 
> > > > > > Hmm there's a gate clock and a mux clock, there's not really a
> > > > > > rate
> > > > > > selection available here for the sources.
> > > > > 
> > > > > If I followed the OMAP driver properly, clk_mux_determine_rate_flags
> > > > > is
> > > > > doing the heavy lifting, could you run your test with
> > > > 
> > > > I'm affected by this patch as well on an imx8mp platform (see [1] for
> > > > some
> > > > details)
> > > > 
> > > > In the failing case with with your patch applied I get the following
> > > > error
> > > > ---
> > > > [    0.661064] clk_set_rate_range_nolock: core req rate 500000000
> > > > [    0.664084] clk_set_rate_range_nolock: clamped rate 500000000
> > > > [    0.669851] clk_core_set_rate_nolock: rate 500000000
> > > > [    0.674843] clk_core_set_rate_nolock: rounded rate 500000000
> > > > [    0.680536] clk_set_rate_range_nolock: core req rate 800000000
> > > > [    0.686389] clk_set_rate_range_nolock: clamped rate 800000000
> > > > [    0.692164] clk_core_set_rate_nolock: rate 800000000
> > > > [    0.697153] clk_mux_determine_rate_flags: requested rate 800000000
> > > > [    0.703363] clk_mux_determine_rate_flags: current parent sys_pll1
> > > > [    0.709487] clk_mux_determine_rate_flags: current parent rate
> > > > 800000000
> > > > [    0.716147] Unable to handle kernel NULL pointer dereference at
> > > > virtual
> > > > address 0000000000000000
> > > > [    0.724977] Mem abort info:
> > > > [    0.727775]   ESR = 0x96000004
> > > > [    0.730835]   EC = 0x25: DABT (current EL), IL = 32 bits
> > > > [    0.736177]   SET = 0, FnV = 0
> > > > [    0.739239]   EA = 0, S1PTW = 0
> > > > [    0.742382]   FSC = 0x04: level 0 translation fault
> > > > [    0.747287] Data abort info:
> > > > [    0.750172]   ISV = 0, ISS = 0x00000004
> > > > [    0.754027]   CM = 0, WnR = 0
> > > > [    0.757002] [0000000000000000] user address but active_mm is
> > > > swapper
> > > > [    0.763394] Internal error: Oops: 96000004 [#1] PREEMPT SMP
> > > > [    0.768985] Modules linked in:
> > > > [    0.772049] CPU: 1 PID: 1 Comm: swapper/0 Not tainted
> > > > 5.17.0-next-20220331+ #48 8e9d24095c7f6b15f85bc2ad57a5609e219130b9
> > > > [    0.782984] Hardware name: TQ-Systems i.MX8MPlus TQMa8MPxL on
> > > > MBa8MPxL
> > > > (DT) [    0.789985] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT
> > > > -SSBS
> > > > BTYPE=--) [    0.796985] pc : clk_mux_determine_rate_flags+0x280/0x2cc
> > > > [    0.802407] lr : clk_mux_determine_rate_flags+0xf4/0x2cc
> > > > [    0.807747] sp : ffff800009ceb590
> > > > [    0.811072] x29: ffff800009ceb590 x28: ffff800009ceb6a0 x27:
> > > > ffff800008eaa038
> > > > [    0.818245] x26: ffff8000092fe0b0 x25: ffff000000090000 x24:
> > > > ffff000000090000
> > > > [    0.825420] x23: 0000000000000000 x22: ffff800008ea95d8 x21:
> > > > ffff0000028f4700
> > > > [    0.832595] x20: 000000002faf0800 x19: 0000000000000000 x18:
> > > > 0000000000004590
> > > > [    0.839770] x17: 0000000000004570 x16: 0000000000004560 x15:
> > > > ffff8000092ff250
> > > > [    0.846945] x14: 0000000000000000 x13: 3030303030303030 x12:
> > > > 3820657461722074
> > > > [    0.854120] x11: 6e6572617020746e x10: 6572727563203a73 x9 :
> > > > 7563203a7367616c
> > > > [    0.861295] x8 : 665f657461725f65 x7 : 205d373834393037 x6 :
> > > > ffff800009a947c8
> > > > [    0.868472] x5 : ffff800008eafe68 x4 : 0000000000000009 x3 :
> > > > 000000002faf0800
> > > > [    0.875645] x2 : ffff800008eafef4 x1 : ffff800008eaa038 x0 :
> > > > ffff8000092fd5b8
> > > > [    0.882822] Call trace:
> > > > [    0.885273]  clk_mux_determine_rate_flags+0x280/0x2cc
> > > > [    0.890347]  clk_mux_determine_rate+0x10/0x20
> > > > [    0.894720]  clk_core_determine_round_nolock+0x4c/0xb4
> > > > [    0.899882]  clk_core_round_rate_nolock+0x30/0x80
> > > > [    0.904607]  clk_core_round_rate_nolock+0x70/0x80
> > > > [    0.909334]  clk_hw_round_rate+0x44/0x74
> > > > [    0.913270]  clk_factor_round_rate+0x60/0x80
> > > > [    0.917557]  clk_core_determine_round_nolock+0x88/0xb4
> > > > [    0.922720]  clk_core_round_rate_nolock+0x30/0x80
> > > > [    0.927445]  clk_core_set_rate_nolock.part.0+0xa4/0x1d0
> > > > [    0.932695]  clk_set_rate_range_nolock+0x234/0x244
> > > > [    0.937507]  __clk_put+0x60/0x12c
> > > > [    0.940834]  clk_put+0xc/0x1c
> > > > [    0.943809]  __set_clk_parents+0x12c/0x244
> > > > [    0.947920]  of_clk_set_defaults+0x20/0x50
> > > > [    0.952032]  of_clk_add_hw_provider.part.0+0x94/0x120
> > > > [    0.957107]  of_clk_add_hw_provider+0x10/0x20
> > > > [    0.961482]  imx8mp_clocks_probe+0x3458/0x34d0
> > > > [    0.965945]  platform_probe+0x64/0x100
> > > > [    0.969707]  call_driver_probe+0x28/0x130
> > > > [    0.973732]  really_probe+0x178/0x310
> > > > [    0.977409]  __driver_probe_device+0xfc/0x144
> > > > [    0.981782]  driver_probe_device+0x38/0x12c
> > > > [    0.985982]  __driver_attach+0xcc/0x220
> > > > [    0.989834]  bus_for_each_dev+0x6c/0xc0
> > > > [    0.993682]  driver_attach+0x20/0x2c
> > > > [    0.997270]  bus_add_driver+0x140/0x230
> > > > [    1.001120]  driver_register+0x74/0x120
> > > > [    1.004970]  __platform_driver_register+0x24/0x30
> > > > [    1.009697]  imx8mp_clk_driver_init+0x18/0x20
> > > > [    1.014070]  do_one_initcall+0x58/0x200
> > > > [    1.017920]  do_initcalls+0x164/0x19c
> > > > [    1.021597]  kernel_init_freeable+0x134/0x17c
> > > > [    1.025970]  kernel_init+0x2c/0x150
> > > > [    1.029470]  ret_from_fork+0x10/0x20
> > > > [    1.033065] Code: f9000f94 912982c1 b0002900 9116e000 (f9400262)
> > > > [    1.039188] ---[ end trace 0000000000000000 ]---
> > > > [    1.043869] Kernel panic - not syncing: Attempted to kill init!
> > > > exitcode=0x0000000b
> > > > [    1.051523] SMP: stopping secondary CPUs
> > > > [    1.055467] Kernel Offset: disabled
> > > > [    1.058960] CPU features: 0x000,00020009,00001082
> > > > [    1.063684] Memory Limit: none
> > > > [    1.066748] ---[ end Kernel panic - not syncing: Attempted to kill
> > > > init!
> > > > exitcode=0x0000000b ]---
> > > > ---
> > > > 
> > > > With the $subject patch reverted and bootable system:
> > > > ---
> > > > [    0.659922] clk_core_set_rate_nolock: rate 1000000000
> > > > [    0.662154] clk_core_set_rate_nolock: rounded rate 1000000000
> > > > [    0.667932] clk_core_set_rate_nolock: rate 800000000
> > > > [    0.672918] clk_core_set_rate_nolock: rounded rate 800000000
> > > > [    0.678601] clk_core_set_rate_nolock: rate 500000000
> > > > [    0.683592] clk_core_set_rate_nolock: rounded rate 500000000
> > > > [    0.689276] clk_core_set_rate_nolock: rate 400000000
> > > > [    0.694267] clk_core_set_rate_nolock: rounded rate 400000000
> > > > [    0.699980] clk_core_set_rate_nolock: rate 800000000
> > > > [    0.704942] clk_core_set_rate_nolock: rounded rate 800000000
> > > > [    0.710627] clk_core_set_rate_nolock: rate 393216000
> > > > [    0.715611] clk_core_set_rate_nolock: rounded rate 393216000
> > > > [    0.721815] clk_core_set_rate_nolock: rate 361267200
> > > > [    0.726284] clk_core_set_rate_nolock: rounded rate 361267200
> > > > [    0.734097] clk_core_set_rate_nolock: rate 800000000
> > > > [    0.736977] clk_core_set_rate_nolock: rounded rate 800000000
> > > > [    0.742652] clk_core_set_rate_nolock: rate 400000000
> > > > [    0.747645] clk_core_set_rate_nolock: rounded rate 400000000
> > > > [    0.754565] clk_core_set_rate_nolock: rate 500000000
> > > > [    0.758331] clk_core_set_rate_nolock: rounded rate 500000000
> > > > [    0.764688] SoC: i.MX8MP revision 1.1
> > > > [    0.767931] clk_core_set_rate_nolock: rate 500000000
> > > > [    0.772675] clk_core_set_rate_nolock: rounded rate 500000000
> > > > [    0.778354] clk_core_set_rate_nolock: rate 200000000
> > > > [    0.783351] clk_core_set_rate_nolock: rounded rate 200000000
> > > > [    0.793748] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
> > > > [    0.798952] 30860000.serial: ttymxc0 at MMIO 0x30860000 (irq = 34,
> > > > base_baud = 5000000) is a IMX
> > > > [    0.806527] 30880000.serial: ttymxc2 at MMIO 0x30880000 (irq = 35,
> > > > base_baud = 5000000) is a IMX
> > > > [    0.815329] 30890000.serial: ttymxc1 at MMIO 0x30890000 (irq = 36,
> > > > base_baud = 5000000) is a IMX
> > > > [    0.824176] 30a60000.serial: ttymxc3 at MMIO 0x30a60000 (irq = 43,
> > > > base_baud = 1500000) is a IMX
> > > > [    0.832588] printk: console [ttymxc3] enabled
> > > > [    0.832588] printk: console [ttymxc3] enabled
> > > > [    0.841244] printk: bootconsole [ec_imx6q0] disabled
> > > > [    0.841244] printk: bootconsole [ec_imx6q0] disabled
> > > > [    0.857871] clk_core_set_rate_nolock: rate 80000000
> > > > [    0.862796] clk_core_set_rate_nolock: rounded rate 80000000
> > > > [    0.868469] clk_core_set_rate_nolock: rate 20000000
> > > > [    0.873364] clk_core_set_rate_nolock: rounded rate 20000000
> > > > [    0.879258] clk_core_set_rate_nolock: rate 80000000
> > > > [    0.884154] clk_core_set_rate_nolock: rounded rate 80000000
> > > > [...]
> > > > ---
> > > > 
> > > > The 500000000 and 800000000 look a bit like the assigned-clock-rates
> > > > for
> > > > clock-controller@30380000 in arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > 
> > > > If you need some more information, do not hesitate to ask
> > > 
> > > Thanks a lot to you three for all your testing. I think I know what
> > > might be going on:
> > > 
> > > We use the last requested rate on clk_set_rate_range
> > > (clk_core.req_rate), and that requested rate if the clock is orphan will
> > > be set to 0, so if we were to call clk_set_rate_range before the parent
> > > clock is registered, we would effectively call a clk_set_rate to 0
> > > 
> > > And the assigned-clocks stuff is handled by __set_clk_parents and
> > > __set_clk_rates, called by of_clk_set_defaults(), in turn called by
> > > of_clk_init and of_clk_add_provider. Both __set_clk_parents and
> > > __set_clk_rates will call clk_put once done with the clock, and we will
> > > with this patch trigger the clk_set_rate to 0 I mentioned before.
> > > 
> > > So we just became very good at triggering the underlying issue :)
> > > 
> > > And I think it's that while we update the requested rate when the
> > > missing parent is registered, we never do when we mux away from it using
> > > clk_set_parent.
> > > 
> > > Could you test the following patch and let me know if it works?
> > > 
> > > --->8---
> > > 
> > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > > index 91f863b7a824..ee5a0223e47d 100644
> > > --- a/drivers/clk/clk.c
> > > +++ b/drivers/clk/clk.c
> > > @@ -2599,6 +2599,8 @@ static int clk_core_set_parent_nolock(struct
> > > clk_core
> > > *core, } else {
> > > 
> > >  		__clk_recalc_rates(core, POST_RATE_CHANGE);
> > >  		__clk_recalc_accuracies(core);
> > > 
> > > +
> > > +		core->req_rate = core->rate;
> > > 
> > >  	}
> > >  
> > >  runtime_put:
> > > --->8---
> > 
> > Thanks for the patch. Unfortunately it does not help in my case. Here is
> > the output form the other patch. It's the same clock (sys_pll1) but a
> > different rate for the first calls.
> > 
> > ---
> > [    0.658706] clk_set_rate_range_nolock: core req rate 800000000
> > [    0.661715] clk_set_rate_range_nolock: clamped rate 800000000
> > [    0.667496] clk_core_set_rate_nolock: rate 800000000
> > [    0.672485] clk_core_set_rate_nolock: rounded rate 800000000
> > [    0.678171] clk_set_rate_range_nolock: core req rate 800000000
> > [    0.684033] clk_set_rate_range_nolock: clamped rate 800000000
> > [    0.689804] clk_core_set_rate_nolock: rate 800000000
> > [    0.694795] clk_mux_determine_rate_flags: requested rate 800000000
> > [    0.701005] clk_mux_determine_rate_flags: current parent sys_pll1
> > [    0.707130] clk_mux_determine_rate_flags: current parent rate 800000000
> > [    0.713789] Unable to handle kernel NULL pointer dereference at virtual
> > address 0000000000000000
> > [    0.722618] Mem abort info:
> > [    0.725411]   ESR = 0x96000004
> > [    0.728483]   EC = 0x25: DABT (current EL), IL = 32 bits
> > [    0.733822]   SET = 0, FnV = 0
> > [    0.736879]   EA = 0, S1PTW = 0
> > [    0.740032]   FSC = 0x04: level 0 translation fault
> > [    0.744930] Data abort info:
> > [    0.747820]   ISV = 0, ISS = 0x00000004
> > [    0.751666]   CM = 0, WnR = 0
> > [    0.754645] [0000000000000000] user address but active_mm is swapper
> > [    0.761034] Internal error: Oops: 96000004 [#1] PREEMPT SMP
> > [    0.766627] Modules linked in:
> > [    0.769690] CPU: 2 PID: 1 Comm: swapper/0 Not tainted
> > 5.17.0-next-20220331+ #51 62b66a4e908a3493b6d37735830c8ba1462e0fc9
> > [    0.780625] Hardware name: TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL
> > (DT) [    0.787627] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS
> > BTYPE=--) [    0.794625] pc : clk_mux_determine_rate_flags+0x280/0x2cc
> > [    0.800049] lr : clk_mux_determine_rate_flags+0xf4/0x2cc
> > [    0.805388] sp : ffff800009ceb590
> > [    0.808713] x29: ffff800009ceb590 x28: ffff800009ceb6a0 x27:
> > ffff800008eaa038
> > [    0.815886] x26: ffff8000092fe090 x25: ffff000000090000 x24:
> > ffff000000090000
> > [    0.823061] x23: 0000000000000000 x22: ffff800008ea95d8 x21:
> > ffff000002aab700
> > [    0.830236] x20: 000000002faf0800 x19: 0000000000000000 x18:
> > 0000000000004590
> > [    0.837411] x17: 0000000000004570 x16: 0000000000004560 x15:
> > ffff8000092ff230
> > [    0.844586] x14: 0000000000000000 x13: 3030303030303030 x12:
> > 3820657461722074
> > [    0.851761] x11: 6e6572617020746e x10: 6572727563203a73 x9 :
> > 7563203a7367616c
> > [    0.858936] x8 : 665f657461725f65 x7 : 205d303331373037 x6 :
> > ffff800009a947c8
> > [    0.866113] x5 : ffff800008eafe68 x4 : 0000000000000009 x3 :
> > 000000002faf0800
> > [    0.873286] x2 : ffff800008eafef4 x1 : ffff800008eaa038 x0 :
> > ffff8000092fd598
> > [    0.880464] Call trace:
> > [    0.882914]  clk_mux_determine_rate_flags+0x280/0x2cc
> > [    0.887989]  clk_mux_determine_rate+0x10/0x20
> > [    0.892361]  clk_core_determine_round_nolock+0x4c/0xb4
> > [    0.897524]  clk_core_round_rate_nolock+0x30/0x80
> > [    0.902249]  clk_core_round_rate_nolock+0x70/0x80
> > [    0.906976]  clk_hw_round_rate+0x44/0x74
> > [    0.910911]  clk_factor_round_rate+0x60/0x80
> > [    0.915199]  clk_core_determine_round_nolock+0x88/0xb4
> > [    0.920361]  clk_core_round_rate_nolock+0x30/0x80
> > [    0.925086]  clk_core_set_rate_nolock.part.0+0xa4/0x1d0
> > [    0.930336]  clk_set_rate_range_nolock+0x234/0x244
> > [    0.935149]  __clk_put+0x60/0x12c
> > [    0.938474]  clk_put+0xc/0x1c
> > [    0.941451]  __set_clk_parents+0x12c/0x244
> > [    0.945561]  of_clk_set_defaults+0x20/0x50
> > [    0.949674]  of_clk_add_hw_provider.part.0+0x94/0x120
> > [    0.954750]  of_clk_add_hw_provider+0x10/0x20
> > [    0.959124]  imx8mp_clocks_probe+0x3458/0x34d0
> > [    0.963586]  platform_probe+0x64/0x100
> > [    0.967349]  call_driver_probe+0x28/0x130
> > [    0.971374]  really_probe+0x178/0x310
> > [    0.975051]  __driver_probe_device+0xfc/0x144
> > [    0.979424]  driver_probe_device+0x38/0x12c
> > [    0.983624]  __driver_attach+0xcc/0x220
> > [    0.987476]  bus_for_each_dev+0x6c/0xc0
> > [    0.991324]  driver_attach+0x20/0x2c
> > [    0.994911]  bus_add_driver+0x140/0x230
> > [    0.998761]  driver_register+0x74/0x120
> > [    1.002611]  __platform_driver_register+0x24/0x30
> > [    1.007338]  imx8mp_clk_driver_init+0x18/0x20
> > [    1.011711]  do_one_initcall+0x58/0x200
> > [    1.015561]  do_initcalls+0x164/0x19c
> > [    1.019238]  kernel_init_freeable+0x134/0x17c
> > [    1.023613]  kernel_init+0x2c/0x150
> > [    1.027111]  ret_from_fork+0x10/0x20
> > [    1.030705] Code: f9000f94 912982c1 d0002900 91166000 (f9400262)
> > [    1.036829] ---[ end trace 0000000000000000 ]---
> > [    1.041512] Kernel panic - not syncing: Attempted to kill init!
> > exitcode=0x0000000b
> > [    1.049164] SMP: stopping secondary CPUs
> > [    1.053108] Kernel Offset: disabled
> > [    1.056600] CPU features: 0x000,00020009,00001082
> > [    1.061326] Memory Limit: none
> > [    1.064390] ---[ end Kernel panic - not syncing: Attempted to kill
> > init!
> > exitcode=0x0000000b ]---
> 
> Does it also happen if you only apply the patch I had above, and not all
> the debugging?

Yes, these are the last lines I see:
---
[    1.236306] mmcblk0rpmb: mmc0:0001 DA6016 4.00 MiB, chardev (235:0)                                                               
[    1.241031] i2c i2c-1: IMX I2C adapter registered                                                                                 
[    1.251771] i2c i2c-3: IMX I2C adapter registered                                                                                 
[    1.256957] i2c i2c-5: IMX I2C adapter registered
---

Alexander

Re: (EXT) Re: (EXT) Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 7198 bytes --]

On Fri, Apr 01, 2022 at 03:07:10PM +0200, Alexander Stein wrote:
> > Does it also happen if you only apply the patch I had above, and not all
> > the debugging?
> 
> Yes, these are the last lines I see:
> ---
> [    1.236306] mmcblk0rpmb: mmc0:0001 DA6016 4.00 MiB, chardev (235:0)                                                               
> [    1.241031] i2c i2c-1: IMX I2C adapter registered                                                                                 
> [    1.251771] i2c i2c-3: IMX I2C adapter registered                                                                                 
> [    1.256957] i2c i2c-5: IMX I2C adapter registered

Could you add on top of next (so dropping everything we did so far)

---- >8 -----
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 91f863b7a824..552b1e16a82d 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -540,6 +540,8 @@ static bool mux_is_better_rate(unsigned long rate, unsigned long now,
 	if (flags & CLK_MUX_ROUND_CLOSEST)
 		return abs(now - rate) < abs(best - rate);

+	pr_crit("%s +%d rate %lu now %lu best %lu\n", __func__, __LINE__, rate, now, best);
+
 	return now <= rate && now > best;
 }

@@ -552,6 +554,12 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
 	unsigned long best = 0;
 	struct clk_rate_request parent_req = *req;

+	pr_crit("%s: %s: requested rate %lu\n", __func__, core->name, req->rate);
+
+	parent = core->parent;
+	pr_crit("%s: %s: current parent %s\n", __func__, core->name, parent ? parent->name : "(null)");
+	pr_crit("%s: %s: current parent rate %lu\n", __func__, core->name, clk_core_get_rate_nolock(parent));
+
 	/* if NO_REPARENT flag set, pass through to current parent */
 	if (core->flags & CLK_SET_RATE_NO_REPARENT) {
 		parent = core->parent;
@@ -578,24 +586,37 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
 		if (!parent)
 			continue;

+		pr_crit("%s: Trying parent %s (%lu)\n",
+			__func__,
+			parent->name,
+			clk_core_get_rate_nolock(parent));
+
 		if (core->flags & CLK_SET_RATE_PARENT) {
+			pr_crit("%s +%d\n", __func__, __LINE__);
 			parent_req = *req;
 			ret = __clk_determine_rate(parent->hw, &parent_req);
+			pr_crit("%s +%d %d\n", __func__, __LINE__, ret);
 			if (ret)
 				continue;
 		} else {
+			pr_crit("%s +%d\n", __func__, __LINE__);
 			parent_req.rate = clk_core_get_rate_nolock(parent);
 		}

+		pr_crit("%s +%d\n", __func__, __LINE__);
+
 		if (mux_is_better_rate(req->rate, parent_req.rate,
 				       best, flags)) {
+			pr_crit("%s +%d\n", __func__, __LINE__);
 			best_parent = parent;
 			best = parent_req.rate;
 		}
 	}

-	if (!best_parent)
+	if (!best_parent) {
+		pr_crit("%s +%d\n", __func__, __LINE__);
 		return -EINVAL;
+	}

 out:
 	if (best_parent)
@@ -603,6 +624,11 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
 	req->best_parent_rate = best;
 	req->rate = best;

+	pr_crit("%s: Best parent %s (%lu)\n",
+		__func__,
+		best_parent->name,
+		best);
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(clk_mux_determine_rate_flags);
@@ -1345,11 +1371,15 @@ static int clk_core_determine_round_nolock(struct clk_core *core,

 	lockdep_assert_held(&prepare_lock);

+	pr_crit("%s +%d %s\n", __func__, __LINE__, core->name);
 	if (!core)
 		return 0;

+	pr_crit("%s +%d\n", __func__, __LINE__);
 	req->rate = clamp(req->rate, req->min_rate, req->max_rate);

+	pr_crit("%s +%d\n", __func__, __LINE__);
+
 	/*
 	 * At this point, core protection will be disabled
 	 * - if the provider is not protected at all
@@ -1357,10 +1387,13 @@ static int clk_core_determine_round_nolock(struct clk_core *core,
 	 *   over the provider
 	 */
 	if (clk_core_rate_is_protected(core)) {
+		pr_crit("%s +%d\n", __func__, __LINE__);
 		req->rate = core->rate;
 	} else if (core->ops->determine_rate) {
+		pr_crit("%s +%d\n", __func__, __LINE__);
 		return core->ops->determine_rate(core->hw, req);
 	} else if (core->ops->round_rate) {
+		pr_crit("%s +%d\n", __func__, __LINE__);
 		rate = core->ops->round_rate(core->hw, req->rate,
 					     &req->best_parent_rate);
 		if (rate < 0)
@@ -1368,6 +1401,7 @@ static int clk_core_determine_round_nolock(struct clk_core *core,

 		req->rate = rate;
 	} else {
+		pr_crit("%s +%d\n", __func__, __LINE__);
 		return -EINVAL;
 	}

@@ -1402,17 +1436,26 @@ static int clk_core_round_rate_nolock(struct clk_core *core,
 {
 	lockdep_assert_held(&prepare_lock);

+	pr_crit("%s +%d\n", __func__, __LINE__);
+
 	if (!core) {
 		req->rate = 0;
 		return 0;
 	}

+	pr_crit("%s +%d\n", __func__, __LINE__);
+
 	clk_core_init_rate_req(core, req);

-	if (clk_core_can_round(core))
+	pr_crit("%s +%d\n", __func__, __LINE__);
+
+	if (clk_core_can_round(core)) {
+		pr_crit("%s +%d\n", __func__, __LINE__);
 		return clk_core_determine_round_nolock(core, req);
-	else if (core->flags & CLK_SET_RATE_PARENT)
+	} else if (core->flags & CLK_SET_RATE_PARENT) {
+		pr_crit("%s +%d\n", __func__, __LINE__);
 		return clk_core_round_rate_nolock(core->parent, req);
+	}

 	req->rate = core->rate;
 	return 0;
@@ -2201,21 +2244,31 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
 	if (!core)
 		return 0;

+	pr_crit("%s: %s: rate %lu\n", __func__, core->name, req_rate);
+
 	rate = clk_core_req_round_rate_nolock(core, req_rate);

+	pr_crit("%s: %s: rounded rate %lu\n", __func__, core->name, req_rate);
+
 	/* bail early if nothing to do */
 	if (rate == clk_core_get_rate_nolock(core))
 		return 0;

+	pr_crit("%s +%d\n", __func__, __LINE__);
+
 	/* fail on a direct rate set of a protected provider */
 	if (clk_core_rate_is_protected(core))
 		return -EBUSY;

+	pr_crit("%s +%d\n", __func__, __LINE__);
+
 	/* calculate new rates and get the topmost changed clock */
 	top = clk_calc_new_rates(core, req_rate);
 	if (!top)
 		return -EINVAL;

+	pr_crit("%s +%d\n", __func__, __LINE__);
+
 	ret = clk_pm_runtime_get(core);
 	if (ret)
 		return ret;
@@ -2367,6 +2420,16 @@ static int clk_set_rate_range_nolock(struct clk *clk,
 		goto out;
 	}

+	pr_crit("%s: %s: orphan ? %c\n",
+		__func__,
+		clk->core->name,
+		clk->core->orphan ? 'y' : 'n');
+
+	pr_crit("%s: %s: core req rate %lu\n",
+		__func__,
+		clk->core->name,
+		clk->core->req_rate);
+
 	/*
 	 * Since the boundaries have been changed, let's give the
 	 * opportunity to the provider to adjust the clock rate based on
@@ -2384,7 +2447,11 @@ static int clk_set_rate_range_nolock(struct clk *clk,
 	 * - the determine_rate() callback does not really check for
 	 *   this corner case when determining the rate
 	 */
+
 	rate = clamp(clk->core->req_rate, min, max);
+
+	pr_crit("%s: %s: clamped rate %lu\n", __func__, clk->core->name, rate);
+
 	ret = clk_core_set_rate_nolock(clk->core, rate);
 	if (ret) {
 		/* rollback the changes */
@@ -2599,6 +2666,8 @@ static int clk_core_set_parent_nolock(struct clk_core *core,
 	} else {
 		__clk_recalc_rates(core, POST_RATE_CHANGE);
 		__clk_recalc_accuracies(core);
+
+		core->req_rate = core->rate;
 	}

 runtime_put:
---- >8 -----

Thanks!
Maxime

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: (EXT) Re: (EXT) Re: (EXT) Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Alexander Stein]

Am Freitag, 1. April 2022, 15:34:09 CEST schrieb Maxime Ripard:
> * PGP Signed by an unknown key
> 
> On Fri, Apr 01, 2022 at 03:07:10PM +0200, Alexander Stein wrote:
> > > Does it also happen if you only apply the patch I had above, and not all
> > > the debugging?
> > 
> > Yes, these are the last lines I see:
> > ---
> > [    1.236306] mmcblk0rpmb: mmc0:0001 DA6016 4.00 MiB, chardev (235:0)
> > [    1.241031] i2c i2c-1: IMX I2C adapter registered
> > [    1.251771] i2c i2c-3: IMX I2C adapter registered
> > [    1.256957] i2c i2c-5: IMX I2C adapter registered
> 
> Could you add on top of next (so dropping everything we did so far)
> 
> ---- >8 -----
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 91f863b7a824..552b1e16a82d 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -540,6 +540,8 @@ static bool mux_is_better_rate(unsigned long rate,
> unsigned long now, if (flags & CLK_MUX_ROUND_CLOSEST)
>  		return abs(now - rate) < abs(best - rate);
> 
> +	pr_crit("%s +%d rate %lu now %lu best %lu\n", __func__, __LINE__, 
rate,
> now, best); +
>  	return now <= rate && now > best;
>  }
> 
> @@ -552,6 +554,12 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
>  	unsigned long best = 0;
>  	struct clk_rate_request parent_req = *req;
> 
> +	pr_crit("%s: %s: requested rate %lu\n", __func__, core->name, req-
>rate);
> +
> +	parent = core->parent;
> +	pr_crit("%s: %s: current parent %s\n", __func__, core->name, parent 
?
> parent->name : "(null)"); +	pr_crit("%s: %s: current parent rate %lu\n",
> __func__, core->name, clk_core_get_rate_nolock(parent)); +
>  	/* if NO_REPARENT flag set, pass through to current parent */
>  	if (core->flags & CLK_SET_RATE_NO_REPARENT) {
>  		parent = core->parent;
> @@ -578,24 +586,37 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
>  		if (!parent)
>  			continue;
> 
> +		pr_crit("%s: Trying parent %s (%lu)\n",
> +			__func__,
> +			parent->name,
> +			clk_core_get_rate_nolock(parent));
> +
>  		if (core->flags & CLK_SET_RATE_PARENT) {
> +			pr_crit("%s +%d\n", __func__, __LINE__);
>  			parent_req = *req;
>  			ret = __clk_determine_rate(parent->hw, 
&parent_req);
> +			pr_crit("%s +%d %d\n", __func__, __LINE__, 
ret);
>  			if (ret)
>  				continue;
>  		} else {
> +			pr_crit("%s +%d\n", __func__, __LINE__);
>  			parent_req.rate = 
clk_core_get_rate_nolock(parent);
>  		}
> 
> +		pr_crit("%s +%d\n", __func__, __LINE__);
> +
>  		if (mux_is_better_rate(req->rate, parent_req.rate,
>  				       best, flags)) {
> +			pr_crit("%s +%d\n", __func__, __LINE__);
>  			best_parent = parent;
>  			best = parent_req.rate;
>  		}
>  	}
> 
> -	if (!best_parent)
> +	if (!best_parent) {
> +		pr_crit("%s +%d\n", __func__, __LINE__);
>  		return -EINVAL;
> +	}
> 
>  out:
>  	if (best_parent)
> @@ -603,6 +624,11 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
>  	req->best_parent_rate = best;
>  	req->rate = best;
> 
> +	pr_crit("%s: Best parent %s (%lu)\n",
> +		__func__,
> +		best_parent->name,
> +		best);
> +
>  	return 0;
>  }
>  EXPORT_SYMBOL_GPL(clk_mux_determine_rate_flags);
> @@ -1345,11 +1371,15 @@ static int clk_core_determine_round_nolock(struct
> clk_core *core,
> 
>  	lockdep_assert_held(&prepare_lock);
> 
> +	pr_crit("%s +%d %s\n", __func__, __LINE__, core->name);
>  	if (!core)
>  		return 0;
> 
> +	pr_crit("%s +%d\n", __func__, __LINE__);
>  	req->rate = clamp(req->rate, req->min_rate, req->max_rate);
> 
> +	pr_crit("%s +%d\n", __func__, __LINE__);
> +
>  	/*
>  	 * At this point, core protection will be disabled
>  	 * - if the provider is not protected at all
> @@ -1357,10 +1387,13 @@ static int clk_core_determine_round_nolock(struct
> clk_core *core, *   over the provider
>  	 */
>  	if (clk_core_rate_is_protected(core)) {
> +		pr_crit("%s +%d\n", __func__, __LINE__);
>  		req->rate = core->rate;
>  	} else if (core->ops->determine_rate) {
> +		pr_crit("%s +%d\n", __func__, __LINE__);
>  		return core->ops->determine_rate(core->hw, req);
>  	} else if (core->ops->round_rate) {
> +		pr_crit("%s +%d\n", __func__, __LINE__);
>  		rate = core->ops->round_rate(core->hw, req->rate,
>  					     &req-
>best_parent_rate);
>  		if (rate < 0)
> @@ -1368,6 +1401,7 @@ static int clk_core_determine_round_nolock(struct
> clk_core *core,
> 
>  		req->rate = rate;
>  	} else {
> +		pr_crit("%s +%d\n", __func__, __LINE__);
>  		return -EINVAL;
>  	}
> 
> @@ -1402,17 +1436,26 @@ static int clk_core_round_rate_nolock(struct
> clk_core *core, {
>  	lockdep_assert_held(&prepare_lock);
> 
> +	pr_crit("%s +%d\n", __func__, __LINE__);
> +
>  	if (!core) {
>  		req->rate = 0;
>  		return 0;
>  	}
> 
> +	pr_crit("%s +%d\n", __func__, __LINE__);
> +
>  	clk_core_init_rate_req(core, req);
> 
> -	if (clk_core_can_round(core))
> +	pr_crit("%s +%d\n", __func__, __LINE__);
> +
> +	if (clk_core_can_round(core)) {
> +		pr_crit("%s +%d\n", __func__, __LINE__);
>  		return clk_core_determine_round_nolock(core, req);
> -	else if (core->flags & CLK_SET_RATE_PARENT)
> +	} else if (core->flags & CLK_SET_RATE_PARENT) {
> +		pr_crit("%s +%d\n", __func__, __LINE__);
>  		return clk_core_round_rate_nolock(core->parent, req);
> +	}
> 
>  	req->rate = core->rate;
>  	return 0;
> @@ -2201,21 +2244,31 @@ static int clk_core_set_rate_nolock(struct clk_core
> *core, if (!core)
>  		return 0;
> 
> +	pr_crit("%s: %s: rate %lu\n", __func__, core->name, req_rate);
> +
>  	rate = clk_core_req_round_rate_nolock(core, req_rate);
> 
> +	pr_crit("%s: %s: rounded rate %lu\n", __func__, core->name, 
req_rate);
> +
>  	/* bail early if nothing to do */
>  	if (rate == clk_core_get_rate_nolock(core))
>  		return 0;
> 
> +	pr_crit("%s +%d\n", __func__, __LINE__);
> +
>  	/* fail on a direct rate set of a protected provider */
>  	if (clk_core_rate_is_protected(core))
>  		return -EBUSY;
> 
> +	pr_crit("%s +%d\n", __func__, __LINE__);
> +
>  	/* calculate new rates and get the topmost changed clock */
>  	top = clk_calc_new_rates(core, req_rate);
>  	if (!top)
>  		return -EINVAL;
> 
> +	pr_crit("%s +%d\n", __func__, __LINE__);
> +
>  	ret = clk_pm_runtime_get(core);
>  	if (ret)
>  		return ret;
> @@ -2367,6 +2420,16 @@ static int clk_set_rate_range_nolock(struct clk *clk,
> goto out;
>  	}
> 
> +	pr_crit("%s: %s: orphan ? %c\n",
> +		__func__,
> +		clk->core->name,
> +		clk->core->orphan ? 'y' : 'n');
> +
> +	pr_crit("%s: %s: core req rate %lu\n",
> +		__func__,
> +		clk->core->name,
> +		clk->core->req_rate);
> +
>  	/*
>  	 * Since the boundaries have been changed, let's give the
>  	 * opportunity to the provider to adjust the clock rate based on
> @@ -2384,7 +2447,11 @@ static int clk_set_rate_range_nolock(struct clk *clk,
> * - the determine_rate() callback does not really check for
>  	 *   this corner case when determining the rate
>  	 */
> +
>  	rate = clamp(clk->core->req_rate, min, max);
> +
> +	pr_crit("%s: %s: clamped rate %lu\n", __func__, clk->core->name, 
rate);
> +
>  	ret = clk_core_set_rate_nolock(clk->core, rate);
>  	if (ret) {
>  		/* rollback the changes */
> @@ -2599,6 +2666,8 @@ static int clk_core_set_parent_nolock(struct clk_core
> *core, } else {
>  		__clk_recalc_rates(core, POST_RATE_CHANGE);
>  		__clk_recalc_accuracies(core);
> +
> +		core->req_rate = core->rate;
>  	}
> 
>  runtime_put:
> ---- >8 -----

Sure, here we go
---
[    0.630873] Asymmetric key parser 'x509' registered                                                                               
[    0.635802] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 
243)                                                  
[    0.643210] io scheduler mq-deadline registered                                                                                   
[    0.647758] io scheduler kyber registered                                                                                         
[    0.658708] clk_set_rate_range_nolock: arm_a53_div: orphan ? n                                                                    
[    0.661717] clk_set_rate_range_nolock: arm_a53_div: core req rate 800000000                                                       
[    0.668724] clk_set_rate_range_nolock: arm_a53_div: clamped rate 800000000                                                        
[    0.675633] clk_core_set_rate_nolock: arm_a53_div: rate 800000000                                                                 
[    0.681761] clk_core_round_rate_nolock +1439                                                                                      
[    0.686048] clk_core_round_rate_nolock +1446                                                                                      
[    0.690333] clk_core_round_rate_nolock +1450                                                                                      
[    0.694619] clk_core_round_rate_nolock +1453                                                                                      
[    0.698908] clk_core_determine_round_nolock +1374 arm_a53_div                                                                     
[    0.704681] clk_core_determine_round_nolock +1378                                                                                 
[    0.709408] clk_core_determine_round_nolock +1381                                                                                 
[    0.714133] clk_core_determine_round_nolock +1393                                                                                 
[    0.718860] clk_core_set_rate_nolock: arm_a53_div: rounded rate 800000000                                                         
[    0.725684] clk_set_rate_range_nolock: sys_pll1_800m: orphan ? n                                                                  
[    0.731719] clk_set_rate_range_nolock: sys_pll1_800m: core req rate 
800000000                                                     
[    0.738894] clk_set_rate_range_nolock: sys_pll1_800m: clamped rate 
800000000                                                      
[    0.745983] clk_core_set_rate_nolock: sys_pll1_800m: rate 800000000                                                               
[    0.752281] clk_core_round_rate_nolock +1439                                                                                      
[    0.756569] clk_core_round_rate_nolock +1446                                                                                      
[    0.760862] clk_core_round_rate_nolock +1450                                                                                      
[    0.765152] clk_core_round_rate_nolock +1453                                                                                      
[    0.769435] clk_core_determine_round_nolock +1374 sys_pll1_800m                                                                   
[    0.775385] clk_core_determine_round_nolock +1378                                                                                 
[    0.780114] clk_core_determine_round_nolock +1381                                                                                 
[    0.784833] clk_core_determine_round_nolock +1396                                                                                 
[    0.789559] clk_core_round_rate_nolock +1439                                                                                      
[    0.793844] clk_core_round_rate_nolock +1446                                                                                      
[    0.798133] clk_core_round_rate_nolock +1450                                                                                      
[    0.802423] clk_core_round_rate_nolock +1456                                                                                      
[    0.806708] clk_core_round_rate_nolock +1439                                                                                      
[    0.810994] clk_core_round_rate_nolock +1446                                                                                      
[    0.815284] clk_core_round_rate_nolock +1450                                                                                      
[    0.819570] clk_core_round_rate_nolock +1453                                                                                      
[    0.823856] clk_core_determine_round_nolock +1374 sys_pll1_bypass                                                                 
[    0.829981] clk_core_determine_round_nolock +1378                                                                                 
[    0.834706] clk_core_determine_round_nolock +1381                                                                                 
[    0.839431] clk_core_determine_round_nolock +1393                                                                                 
[    0.844159] clk_mux_determine_rate_flags: sys_pll1_bypass: requested rate 
800000000                                               
[    0.851856] clk_mux_determine_rate_flags: sys_pll1_bypass: current parent 
sys_pll1                                                
[    0.859471] clk_mux_determine_rate_flags: sys_pll1_bypass: current parent 
rate 800000000                                          
[    0.867608] clk_core_round_rate_nolock +1439                                                                                      
[    0.871894] clk_core_round_rate_nolock +1446                                                                                      
[    0.876182] clk_core_round_rate_nolock +1450                                                                                      
[    0.880477] clk_core_round_rate_nolock +1453                                                                                      
[    0.884758] clk_core_determine_round_nolock +1374 sys_pll1                                                                        
[    0.890273] clk_core_determine_round_nolock +1378                                                                                 
[    0.894996] clk_core_determine_round_nolock +1381                                                                                 
[    0.899721] clk_core_determine_round_nolock +1396                                                                                 
[    0.904457] Unable to handle kernel NULL pointer dereference at virtual 
address 0000000000000000                                  
[    0.913285] Mem abort info:                                                                                                       
[    0.916083]   ESR = 0x96000004                                                                                                    
[    0.919147]   EC = 0x25: DABT (current EL), IL = 32 bits                                                                          
[    0.924484]   SET = 0, FnV = 0                                                                                                    
[    0.927547]   EA = 0, S1PTW = 0                                                                                                   
[    0.930697]   FSC = 0x04: level 0 translation fault
[    0.935595] Data abort info:
[    0.938487]   ISV = 0, ISS = 0x00000004
[    0.942334]   CM = 0, WnR = 0
[    0.945304] [0000000000000000] user address but active_mm is swapper
[    0.951696] Internal error: Oops: 96000004 [#1] PREEMPT SMP
[    0.957292] Modules linked in:
[    0.960355] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.17.0-next-20220331+ 
#53 da834fe2485dc10e4c2f50265323ce628a30bc5e
[    0.971291] Hardware name: TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL (DT)
[    0.978292] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[    0.985291] pc : clk_mux_determine_rate_flags+0x33c/0x380
[    0.990714] lr : clk_mux_determine_rate_flags+0x10c/0x380
[    0.996141] sp : ffff800009ceb4a0
[    0.999464] x29: ffff800009ceb4a0 x28: ffff000002cf4700 x27: 
0000000000000001
[    1.006639] x26: ffff8000092fe728 x25: ffff800008eaa028 x24: 
ffff800008ea95d8
[    1.013816] x23: ffff800008ea95d8 x22: ffff000002aab700 x21: 
000000002faf0800
[    1.020989] x20: ffff800009ceb640 x19: 0000000000000000 x18: 
0000000000004590
[    1.028164] x17: 617220746e657261 x16: 7020746e65727275 x15: 
63203a7373617079
[    1.035339] x14: 0000000000000000 x13: 363933312b206b63 x12: 
6f6c6f6e5f646e75
[    1.042514] x11: 6f725f656e696d72 x10: 657465645f65726f x9 : 
206b636f6c6f6e5f
[    1.049689] x8 : 646e756f725f656e x7 : 205d313237393938 x6 : 
ffff800009a947c8
[    1.056864] x5 : ffff800008eb0310 x4 : 0000000000000009 x3 : 
000000002faf0800
[    1.064039] x2 : ffff800008eb039c x1 : ffff800008eaa028 x0 : 
ffff8000092fd8b8
[    1.071217] Call trace:
[    1.073667]  clk_mux_determine_rate_flags+0x33c/0x380
[    1.078741]  clk_mux_determine_rate+0x10/0x20
[    1.083115]  clk_core_determine_round_nolock+0xd4/0x140
[    1.088364]  clk_core_round_rate_nolock+0xac/0xf8
[    1.093090]  clk_core_round_rate_nolock+0xd4/0xf8
[    1.097814]  clk_hw_round_rate+0x44/0x7c
[    1.101751]  clk_factor_round_rate+0x60/0x80
[    1.106041]  clk_core_determine_round_nolock+0x104/0x140
[    1.111376]  clk_core_round_rate_nolock+0xac/0xf8
[    1.116101]  clk_core_set_rate_nolock.part.0+0xac/0x21c
[    1.121351]  clk_set_rate_range_nolock+0x294/0x2b0
[    1.126164]  __clk_put+0x60/0x12c
[    1.129489]  clk_put+0xc/0x1c
[    1.132464]  __set_clk_parents+0x12c/0x244
[    1.136576]  of_clk_set_defaults+0x20/0x50
[    1.140691]  of_clk_add_hw_provider.part.0+0x94/0x120
[    1.145764]  of_clk_add_hw_provider+0x10/0x20
[    1.150139]  imx8mp_clocks_probe+0x3458/0x34d0
[    1.154601]  platform_probe+0x64/0x100
[    1.158364]  call_driver_probe+0x28/0x130
[    1.162389]  really_probe+0x178/0x310
[    1.166064]  __driver_probe_device+0xfc/0x144
[    1.170439]  driver_probe_device+0x38/0x12c
[    1.174641]  __driver_attach+0xcc/0x220
[    1.178489]  bus_for_each_dev+0x6c/0xc0
[    1.182339]  driver_attach+0x20/0x2c
[    1.185926]  bus_add_driver+0x140/0x230
[    1.189776]  driver_register+0x74/0x120
[    1.193626]  __platform_driver_register+0x24/0x30
[    1.198351]  imx8mp_clk_driver_init+0x18/0x20
[    1.202726]  do_one_initcall+0x58/0x200
[    1.206578]  do_initcalls+0x164/0x19c
[    1.210251]  kernel_init_freeable+0x134/0x17c
[    1.214628]  kernel_init+0x2c/0x150
[    1.218126]  ret_from_fork+0x10/0x20
[    1.221720] Code: f9000e95 91294301 d0002900 9122e000 (f9400262) 
[    1.227845] ---[ end trace 0000000000000000 ]---
[    1.232501] Kernel panic - not syncing: Attempted to kill init! 
exitcode=0x0000000b
[    1.240179] SMP: stopping secondary CPUs
[    1.244122] Kernel Offset: disabled
[    1.247616] CPU features: 0x000,00020009,00001082
[    1.252341] Memory Limit: none
[    1.255406] ---[ end Kernel panic - not syncing: Attempted to kill init! 
exitcode=0x0000000b ]---
---

HTH
Alexander

Re: (EXT) Re: (EXT) Re: (EXT) Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 16891 bytes --]

On Fri, Apr 01, 2022 at 03:49:04PM +0200, Alexander Stein wrote:
> Am Freitag, 1. April 2022, 15:34:09 CEST schrieb Maxime Ripard:
> > * PGP Signed by an unknown key
> > 
> > On Fri, Apr 01, 2022 at 03:07:10PM +0200, Alexander Stein wrote:
> > > > Does it also happen if you only apply the patch I had above, and not all
> > > > the debugging?
> > > 
> > > Yes, these are the last lines I see:
> > > ---
> > > [    1.236306] mmcblk0rpmb: mmc0:0001 DA6016 4.00 MiB, chardev (235:0)
> > > [    1.241031] i2c i2c-1: IMX I2C adapter registered
> > > [    1.251771] i2c i2c-3: IMX I2C adapter registered
> > > [    1.256957] i2c i2c-5: IMX I2C adapter registered
> > 
> > Could you add on top of next (so dropping everything we did so far)
> > 
> > ---- >8 -----
> > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > index 91f863b7a824..552b1e16a82d 100644
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -540,6 +540,8 @@ static bool mux_is_better_rate(unsigned long rate,
> > unsigned long now, if (flags & CLK_MUX_ROUND_CLOSEST)
> >  		return abs(now - rate) < abs(best - rate);
> > 
> > +	pr_crit("%s +%d rate %lu now %lu best %lu\n", __func__, __LINE__, 
> rate,
> > now, best); +
> >  	return now <= rate && now > best;
> >  }
> > 
> > @@ -552,6 +554,12 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
> >  	unsigned long best = 0;
> >  	struct clk_rate_request parent_req = *req;
> > 
> > +	pr_crit("%s: %s: requested rate %lu\n", __func__, core->name, req-
> >rate);
> > +
> > +	parent = core->parent;
> > +	pr_crit("%s: %s: current parent %s\n", __func__, core->name, parent 
> ?
> > parent->name : "(null)"); +	pr_crit("%s: %s: current parent rate %lu\n",
> > __func__, core->name, clk_core_get_rate_nolock(parent)); +
> >  	/* if NO_REPARENT flag set, pass through to current parent */
> >  	if (core->flags & CLK_SET_RATE_NO_REPARENT) {
> >  		parent = core->parent;
> > @@ -578,24 +586,37 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
> >  		if (!parent)
> >  			continue;
> > 
> > +		pr_crit("%s: Trying parent %s (%lu)\n",
> > +			__func__,
> > +			parent->name,
> > +			clk_core_get_rate_nolock(parent));
> > +
> >  		if (core->flags & CLK_SET_RATE_PARENT) {
> > +			pr_crit("%s +%d\n", __func__, __LINE__);
> >  			parent_req = *req;
> >  			ret = __clk_determine_rate(parent->hw, 
> &parent_req);
> > +			pr_crit("%s +%d %d\n", __func__, __LINE__, 
> ret);
> >  			if (ret)
> >  				continue;
> >  		} else {
> > +			pr_crit("%s +%d\n", __func__, __LINE__);
> >  			parent_req.rate = 
> clk_core_get_rate_nolock(parent);
> >  		}
> > 
> > +		pr_crit("%s +%d\n", __func__, __LINE__);
> > +
> >  		if (mux_is_better_rate(req->rate, parent_req.rate,
> >  				       best, flags)) {
> > +			pr_crit("%s +%d\n", __func__, __LINE__);
> >  			best_parent = parent;
> >  			best = parent_req.rate;
> >  		}
> >  	}
> > 
> > -	if (!best_parent)
> > +	if (!best_parent) {
> > +		pr_crit("%s +%d\n", __func__, __LINE__);
> >  		return -EINVAL;
> > +	}
> > 
> >  out:
> >  	if (best_parent)
> > @@ -603,6 +624,11 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
> >  	req->best_parent_rate = best;
> >  	req->rate = best;
> > 
> > +	pr_crit("%s: Best parent %s (%lu)\n",
> > +		__func__,
> > +		best_parent->name,
> > +		best);
> > +
> >  	return 0;
> >  }
> >  EXPORT_SYMBOL_GPL(clk_mux_determine_rate_flags);
> > @@ -1345,11 +1371,15 @@ static int clk_core_determine_round_nolock(struct
> > clk_core *core,
> > 
> >  	lockdep_assert_held(&prepare_lock);
> > 
> > +	pr_crit("%s +%d %s\n", __func__, __LINE__, core->name);
> >  	if (!core)
> >  		return 0;
> > 
> > +	pr_crit("%s +%d\n", __func__, __LINE__);
> >  	req->rate = clamp(req->rate, req->min_rate, req->max_rate);
> > 
> > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > +
> >  	/*
> >  	 * At this point, core protection will be disabled
> >  	 * - if the provider is not protected at all
> > @@ -1357,10 +1387,13 @@ static int clk_core_determine_round_nolock(struct
> > clk_core *core, *   over the provider
> >  	 */
> >  	if (clk_core_rate_is_protected(core)) {
> > +		pr_crit("%s +%d\n", __func__, __LINE__);
> >  		req->rate = core->rate;
> >  	} else if (core->ops->determine_rate) {
> > +		pr_crit("%s +%d\n", __func__, __LINE__);
> >  		return core->ops->determine_rate(core->hw, req);
> >  	} else if (core->ops->round_rate) {
> > +		pr_crit("%s +%d\n", __func__, __LINE__);
> >  		rate = core->ops->round_rate(core->hw, req->rate,
> >  					     &req-
> >best_parent_rate);
> >  		if (rate < 0)
> > @@ -1368,6 +1401,7 @@ static int clk_core_determine_round_nolock(struct
> > clk_core *core,
> > 
> >  		req->rate = rate;
> >  	} else {
> > +		pr_crit("%s +%d\n", __func__, __LINE__);
> >  		return -EINVAL;
> >  	}
> > 
> > @@ -1402,17 +1436,26 @@ static int clk_core_round_rate_nolock(struct
> > clk_core *core, {
> >  	lockdep_assert_held(&prepare_lock);
> > 
> > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > +
> >  	if (!core) {
> >  		req->rate = 0;
> >  		return 0;
> >  	}
> > 
> > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > +
> >  	clk_core_init_rate_req(core, req);
> > 
> > -	if (clk_core_can_round(core))
> > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > +
> > +	if (clk_core_can_round(core)) {
> > +		pr_crit("%s +%d\n", __func__, __LINE__);
> >  		return clk_core_determine_round_nolock(core, req);
> > -	else if (core->flags & CLK_SET_RATE_PARENT)
> > +	} else if (core->flags & CLK_SET_RATE_PARENT) {
> > +		pr_crit("%s +%d\n", __func__, __LINE__);
> >  		return clk_core_round_rate_nolock(core->parent, req);
> > +	}
> > 
> >  	req->rate = core->rate;
> >  	return 0;
> > @@ -2201,21 +2244,31 @@ static int clk_core_set_rate_nolock(struct clk_core
> > *core, if (!core)
> >  		return 0;
> > 
> > +	pr_crit("%s: %s: rate %lu\n", __func__, core->name, req_rate);
> > +
> >  	rate = clk_core_req_round_rate_nolock(core, req_rate);
> > 
> > +	pr_crit("%s: %s: rounded rate %lu\n", __func__, core->name, 
> req_rate);
> > +
> >  	/* bail early if nothing to do */
> >  	if (rate == clk_core_get_rate_nolock(core))
> >  		return 0;
> > 
> > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > +
> >  	/* fail on a direct rate set of a protected provider */
> >  	if (clk_core_rate_is_protected(core))
> >  		return -EBUSY;
> > 
> > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > +
> >  	/* calculate new rates and get the topmost changed clock */
> >  	top = clk_calc_new_rates(core, req_rate);
> >  	if (!top)
> >  		return -EINVAL;
> > 
> > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > +
> >  	ret = clk_pm_runtime_get(core);
> >  	if (ret)
> >  		return ret;
> > @@ -2367,6 +2420,16 @@ static int clk_set_rate_range_nolock(struct clk *clk,
> > goto out;
> >  	}
> > 
> > +	pr_crit("%s: %s: orphan ? %c\n",
> > +		__func__,
> > +		clk->core->name,
> > +		clk->core->orphan ? 'y' : 'n');
> > +
> > +	pr_crit("%s: %s: core req rate %lu\n",
> > +		__func__,
> > +		clk->core->name,
> > +		clk->core->req_rate);
> > +
> >  	/*
> >  	 * Since the boundaries have been changed, let's give the
> >  	 * opportunity to the provider to adjust the clock rate based on
> > @@ -2384,7 +2447,11 @@ static int clk_set_rate_range_nolock(struct clk *clk,
> > * - the determine_rate() callback does not really check for
> >  	 *   this corner case when determining the rate
> >  	 */
> > +
> >  	rate = clamp(clk->core->req_rate, min, max);
> > +
> > +	pr_crit("%s: %s: clamped rate %lu\n", __func__, clk->core->name, 
> rate);
> > +
> >  	ret = clk_core_set_rate_nolock(clk->core, rate);
> >  	if (ret) {
> >  		/* rollback the changes */
> > @@ -2599,6 +2666,8 @@ static int clk_core_set_parent_nolock(struct clk_core
> > *core, } else {
> >  		__clk_recalc_rates(core, POST_RATE_CHANGE);
> >  		__clk_recalc_accuracies(core);
> > +
> > +		core->req_rate = core->rate;
> >  	}
> > 
> >  runtime_put:
> > ---- >8 -----

So, let's try to follow this through:

> Sure, here we go
> ---
> [    0.630873] Asymmetric key parser 'x509' registered
> [    0.635802] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
> [    0.643210] io scheduler mq-deadline registered
> [    0.647758] io scheduler kyber registered
> [    0.658708] clk_set_rate_range_nolock: arm_a53_div: orphan ? n
> [    0.661717] clk_set_rate_range_nolock: arm_a53_div: core req rate 800000000
> [    0.668724] clk_set_rate_range_nolock: arm_a53_div: clamped rate 800000000

I'm assuming we hit the assigned-clock-parents in the clocks node, and
we try to reparent arm_a53_div / IMX8MP_CLK_A53_SRC to sys_pll1_800m

I'm not entirely sure, but it looks like the arm_a53_div is a gate +
divider, so that it has the same rate than its parent makes sens, and
800MHz for a CPU clock also makes sense.

It's also not an orphan, so it's likely to be a separate issue from Tony
(and thus the fix doesn't help, sorry).

> [    0.675633] clk_core_set_rate_nolock: arm_a53_div: rate 800000000

Now, we set the rate to the same rate, this still makes sense.

> [    0.681761] clk_core_round_rate_nolock +1439
> [    0.686048] clk_core_round_rate_nolock +1446
> [    0.690333] clk_core_round_rate_nolock +1450
> [    0.694619] clk_core_round_rate_nolock +1453
> [    0.698908] clk_core_determine_round_nolock +1374 arm_a53_div

The clock has a round_rate / determine_rate implementation
(clk_divider_round_rate, most likely), thus we call
clk_core_determine_round_nolock()

> [    0.704681] clk_core_determine_round_nolock +1378
> [    0.709408] clk_core_determine_round_nolock +1381
> [    0.714133] clk_core_determine_round_nolock +1393

Still on the right path, we use clk_divider_determine_rate (too bad :)),
it updates the rate

> [    0.718860] clk_core_set_rate_nolock: arm_a53_div: rounded rate 800000000

But it didn't change, good. The rounded clock hasn't changed,
clk_core_set_rate_nolock returns, everything's great.

> [    0.725684] clk_set_rate_range_nolock: sys_pll1_800m: orphan ? n
> [    0.731719] clk_set_rate_range_nolock: sys_pll1_800m: core req rate 800000000
> [    0.738894] clk_set_rate_range_nolock: sys_pll1_800m: clamped rate 800000000
> [    0.745983] clk_core_set_rate_nolock: sys_pll1_800m: rate 800000000

Then, __set_clk_parents calls clk_put() on the new parent,
sys_pll1_800m, still not an orphan, still with a rate that makes sense.

> [    0.752281] clk_core_round_rate_nolock +1439
> [    0.756569] clk_core_round_rate_nolock +1446
> [    0.760862] clk_core_round_rate_nolock +1450
> [    0.765152] clk_core_round_rate_nolock +1453
> [    0.769435] clk_core_determine_round_nolock +1374 sys_pll1_800m

We still can round the rate, so we go to
clk_core_determine_round_nolock()

> [    0.775385] clk_core_determine_round_nolock +1378
> [    0.780114] clk_core_determine_round_nolock +1381
> [    0.784833] clk_core_determine_round_nolock +1396

But this time using a round_rate implementation: clk_factor_round_rate
(since sys_pll1_800m is a "pure" fixed factor clock). It has the flag
CLK_SET_RATE_PARENT (set in imx_clk_hw_fixed_factor), so
clk_factor_round_rate calls clk_hw_round_rate on its parent
(sys_pll1_out) for the same rate since it has a factor of 1.

> [    0.789559] clk_core_round_rate_nolock +1439
> [    0.793844] clk_core_round_rate_nolock +1446
> [    0.798133] clk_core_round_rate_nolock +1450
> [    0.802423] clk_core_round_rate_nolock +1456

We go through another round_rate cycle here, for sys_pll1_out. It can't
modify the rate (since it's a gate) but it has CLK_SET_RATE_PARENT, so
the rate rounding is forwarded to its parent: sys_pll1_bypass.

> [    0.806708] clk_core_round_rate_nolock +1439
> [    0.810994] clk_core_round_rate_nolock +1446
> [    0.815284] clk_core_round_rate_nolock +1450
> [    0.819570] clk_core_round_rate_nolock +1453

We go through it, and call clk_core_determine_round_nolock again for
sys_pll1_bypass.

> [    0.823856] clk_core_determine_round_nolock +1374 sys_pll1_bypass

Makes total sense so far.

> [    0.829981] clk_core_determine_round_nolock +1378
> [    0.834706] clk_core_determine_round_nolock +1381
> [    0.839431] clk_core_determine_round_nolock +1393
> [    0.844159] clk_mux_determine_rate_flags: sys_pll1_bypass: requested rate 800000000

The requested rate does too. We still have our 800MHz.

> [    0.851856] clk_mux_determine_rate_flags: sys_pll1_bypass: current parent sys_pll1
> [    0.859471] clk_mux_determine_rate_flags: sys_pll1_bypass: current parent rate 800000000

sys_pll1_bypass has CLK_SET_RATE_NO_REPARENT (set by __imx_clk_hw_mux)
and CLK_SET_RATE_PARENT (set by the driver when registering the clock),
so clk_mux_determine_rate_flags will call __clk_determine_rate on its
parent: sys_pll1. __clk_determine_rate then calls
clk_core_round_rate_nolock.

> [    0.867608] clk_core_round_rate_nolock +1439
> [    0.871894] clk_core_round_rate_nolock +1446
> [    0.876182] clk_core_round_rate_nolock +1450
> [    0.880477] clk_core_round_rate_nolock +1453

We call clk_core_determine_round_nolock on sys_pll1

> [    0.884758] clk_core_determine_round_nolock +1374 sys_pll1
> [    0.890273] clk_core_determine_round_nolock +1378
> [    0.894996] clk_core_determine_round_nolock +1381
> [    0.899721] clk_core_determine_round_nolock +1396

sys_pll1 is a clk_pll14xx driver, it has a PLL_1416X type and a rate
table, so it will use clk_pll1416x_ops. It has a round_rate
implementation, clk_pll14xx_round_rate, that doesn't seem to be doing
anything out of the ordinary. My assumption would be that it succeeds
and returns a proper rate.

> [    0.904457] Unable to handle kernel NULL pointer dereference at virtual 
> address 0000000000000000
> [    0.913285] Mem abort info:
> [    0.916083]   ESR = 0x96000004
> [    0.919147]   EC = 0x25: DABT (current EL), IL = 32 bits
> [    0.924484]   SET = 0, FnV = 0
> [    0.927547]   EA = 0, S1PTW = 0
> [    0.930697]   FSC = 0x04: level 0 translation fault
> [    0.935595] Data abort info:
> [    0.938487]   ISV = 0, ISS = 0x00000004
> [    0.942334]   CM = 0, WnR = 0
> [    0.945304] [0000000000000000] user address but active_mm is swapper
> [    0.951696] Internal error: Oops: 96000004 [#1] PREEMPT SMP
> [    0.957292] Modules linked in:
> [    0.960355] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.17.0-next-20220331+
> #53 da834fe2485dc10e4c2f50265323ce628a30bc5e
> [    0.971291] Hardware name: TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL (DT)
> [    0.978292] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [    0.985291] pc : clk_mux_determine_rate_flags+0x33c/0x380
> [    0.990714] lr : clk_mux_determine_rate_flags+0x10c/0x380
> [    0.996141] sp : ffff800009ceb4a0
> [    0.999464] x29: ffff800009ceb4a0 x28: ffff000002cf4700 x27:
> 0000000000000001
> [    1.006639] x26: ffff8000092fe728 x25: ffff800008eaa028 x24:
> ffff800008ea95d8
> [    1.013816] x23: ffff800008ea95d8 x22: ffff000002aab700 x21:
> 000000002faf0800
> [    1.020989] x20: ffff800009ceb640 x19: 0000000000000000 x18:
> 0000000000004590
> [    1.028164] x17: 617220746e657261 x16: 7020746e65727275 x15:
> 63203a7373617079
> [    1.035339] x14: 0000000000000000 x13: 363933312b206b63 x12:
> 6f6c6f6e5f646e75
> [    1.042514] x11: 6f725f656e696d72 x10: 657465645f65726f x9 :
> 206b636f6c6f6e5f
> [    1.049689] x8 : 646e756f725f656e x7 : 205d313237393938 x6 :
> ffff800009a947c8
> [    1.056864] x5 : ffff800008eb0310 x4 : 0000000000000009 x3 :
> 000000002faf0800
> [    1.064039] x2 : ffff800008eb039c x1 : ffff800008eaa028 x0 :
> ffff8000092fd8b8
> [    1.071217] Call trace:
> [    1.073667]  clk_mux_determine_rate_flags+0x33c/0x380
> [    1.078741]  clk_mux_determine_rate+0x10/0x20
> [    1.083115]  clk_core_determine_round_nolock+0xd4/0x140
> [    1.088364]  clk_core_round_rate_nolock+0xac/0xf8
> [    1.093090]  clk_core_round_rate_nolock+0xd4/0xf8
> [    1.097814]  clk_hw_round_rate+0x44/0x7c
> [    1.101751]  clk_factor_round_rate+0x60/0x80
> [    1.106041]  clk_core_determine_round_nolock+0x104/0x140
> [    1.111376]  clk_core_round_rate_nolock+0xac/0xf8
> [    1.116101]  clk_core_set_rate_nolock.part.0+0xac/0x21c
> [    1.121351]  clk_set_rate_range_nolock+0x294/0x2b0

But then, where does this come from?

I'm not entirely sure, but the walk up the clock tree is sane to me.
Could you run

./scripts/faddr2line vmlinux 'clk_mux_determine_rate_flags+0x33c/0x380'

in your kernel compilation directory? (with ARCH and CROSS_COMPILE set
if you're doing cross-compilation)?

My guess would be that we uncovered some other bug there, but I'm not
sure what exactly.

Maxime

[-- Attachment #2: signature.asc --]
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Re: (EXT) Re: (EXT) Re: (EXT) Re: (EXT) Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Alexander Stein]

Hello Maxime,

Am Freitag, 1. April 2022, 16:55:02 CEST schrieb Maxime Ripard:
> * PGP Signed by an unknown key
> 
> On Fri, Apr 01, 2022 at 03:49:04PM +0200, Alexander Stein wrote:
> > Am Freitag, 1. April 2022, 15:34:09 CEST schrieb Maxime Ripard:
> > > > Old Signed by an unknown key
> > > 
> > > On Fri, Apr 01, 2022 at 03:07:10PM +0200, Alexander Stein wrote:
> > > > > Does it also happen if you only apply the patch I had above, and not
> > > > > all
> > > > > the debugging?
> > > > 
> > > > Yes, these are the last lines I see:
> > > > ---
> > > > [    1.236306] mmcblk0rpmb: mmc0:0001 DA6016 4.00 MiB, chardev (235:0)
> > > > [    1.241031] i2c i2c-1: IMX I2C adapter registered
> > > > [    1.251771] i2c i2c-3: IMX I2C adapter registered
> > > > [    1.256957] i2c i2c-5: IMX I2C adapter registered
> > > 
> > > Could you add on top of next (so dropping everything we did so far)
> > > 
> > > ---- >8 -----
> > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > > index 91f863b7a824..552b1e16a82d 100644
> > > --- a/drivers/clk/clk.c
> > > +++ b/drivers/clk/clk.c
> > > @@ -540,6 +540,8 @@ static bool mux_is_better_rate(unsigned long rate,
> > > unsigned long now, if (flags & CLK_MUX_ROUND_CLOSEST)
> > > 
> > >  		return abs(now - rate) < abs(best - rate);
> > > 
> > > +	pr_crit("%s +%d rate %lu now %lu best %lu\n", __func__, __LINE__,
> > 
> > rate,
> > 
> > > now, best); +
> > > 
> > >  	return now <= rate && now > best;
> > >  
> > >  }
> > > 
> > > @@ -552,6 +554,12 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
> > > 
> > >  	unsigned long best = 0;
> > >  	struct clk_rate_request parent_req = *req;
> > > 
> > > +	pr_crit("%s: %s: requested rate %lu\n", __func__, core->name, req-
> > >
> > >rate);
> > >
> > > +
> > > +	parent = core->parent;
> > > +	pr_crit("%s: %s: current parent %s\n", __func__, core->name, parent
> > 
> > ?
> > 
> > > parent->name : "(null)"); +	pr_crit("%s: %s: current parent rate %lu\n",
> > > __func__, core->name, clk_core_get_rate_nolock(parent)); +
> > > 
> > >  	/* if NO_REPARENT flag set, pass through to current parent */
> > >  	if (core->flags & CLK_SET_RATE_NO_REPARENT) {
> > >  	
> > >  		parent = core->parent;
> > > 
> > > @@ -578,24 +586,37 @@ int clk_mux_determine_rate_flags(struct clk_hw
> > > *hw,
> > > 
> > >  		if (!parent)
> > >  		
> > >  			continue;
> > > 
> > > +		pr_crit("%s: Trying parent %s (%lu)\n",
> > > +			__func__,
> > > +			parent->name,
> > > +			clk_core_get_rate_nolock(parent));
> > > +
> > > 
> > >  		if (core->flags & CLK_SET_RATE_PARENT) {
> > > 
> > > +			pr_crit("%s +%d\n", __func__, __LINE__);
> > > 
> > >  			parent_req = *req;
> > >  			ret = __clk_determine_rate(parent->hw,
> > 
> > &parent_req);
> > 
> > > +			pr_crit("%s +%d %d\n", __func__, __LINE__,
> > 
> > ret);
> > 
> > >  			if (ret)
> > >  			
> > >  				continue;
> > >  		
> > >  		} else {
> > > 
> > > +			pr_crit("%s +%d\n", __func__, __LINE__);
> > > 
> > >  			parent_req.rate =
> > 
> > clk_core_get_rate_nolock(parent);
> > 
> > >  		}
> > > 
> > > +		pr_crit("%s +%d\n", __func__, __LINE__);
> > > +
> > > 
> > >  		if (mux_is_better_rate(req->rate, parent_req.rate,
> > >  		
> > >  				       best, flags)) {
> > > 
> > > +			pr_crit("%s +%d\n", __func__, __LINE__);
> > > 
> > >  			best_parent = parent;
> > >  			best = parent_req.rate;
> > >  		
> > >  		}
> > >  	
> > >  	}
> > > 
> > > -	if (!best_parent)
> > > +	if (!best_parent) {
> > > +		pr_crit("%s +%d\n", __func__, __LINE__);
> > > 
> > >  		return -EINVAL;
> > > 
> > > +	}
> > > 
> > >  out:
> > >  	if (best_parent)
> > > 
> > > @@ -603,6 +624,11 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
> > > 
> > >  	req->best_parent_rate = best;
> > >  	req->rate = best;
> > > 
> > > +	pr_crit("%s: Best parent %s (%lu)\n",
> > > +		__func__,
> > > +		best_parent->name,
> > > +		best);
> > > +
> > > 
> > >  	return 0;
> > >  
> > >  }
> > >  EXPORT_SYMBOL_GPL(clk_mux_determine_rate_flags);
> > > 
> > > @@ -1345,11 +1371,15 @@ static int
> > > clk_core_determine_round_nolock(struct
> > > clk_core *core,
> > > 
> > >  	lockdep_assert_held(&prepare_lock);
> > > 
> > > +	pr_crit("%s +%d %s\n", __func__, __LINE__, core->name);
> > > 
> > >  	if (!core)
> > >  	
> > >  		return 0;
> > > 
> > > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > > 
> > >  	req->rate = clamp(req->rate, req->min_rate, req->max_rate);
> > > 
> > > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > > +
> > > 
> > >  	/*
> > >  	
> > >  	 * At this point, core protection will be disabled
> > >  	 * - if the provider is not protected at all
> > > 
> > > @@ -1357,10 +1387,13 @@ static int
> > > clk_core_determine_round_nolock(struct
> > > clk_core *core, *   over the provider
> > > 
> > >  	 */
> > >  	
> > >  	if (clk_core_rate_is_protected(core)) {
> > > 
> > > +		pr_crit("%s +%d\n", __func__, __LINE__);
> > > 
> > >  		req->rate = core->rate;
> > >  	
> > >  	} else if (core->ops->determine_rate) {
> > > 
> > > +		pr_crit("%s +%d\n", __func__, __LINE__);
> > > 
> > >  		return core->ops->determine_rate(core->hw, req);
> > >  	
> > >  	} else if (core->ops->round_rate) {
> > > 
> > > +		pr_crit("%s +%d\n", __func__, __LINE__);
> > > 
> > >  		rate = core->ops->round_rate(core->hw, req->rate,
> > >  		
> > >  					     &req-
> > >
> > >best_parent_rate);
> > >
> > >  		if (rate < 0)
> > > 
> > > @@ -1368,6 +1401,7 @@ static int clk_core_determine_round_nolock(struct
> > > clk_core *core,
> > > 
> > >  		req->rate = rate;
> > >  	
> > >  	} else {
> > > 
> > > +		pr_crit("%s +%d\n", __func__, __LINE__);
> > > 
> > >  		return -EINVAL;
> > >  	
> > >  	}
> > > 
> > > @@ -1402,17 +1436,26 @@ static int clk_core_round_rate_nolock(struct
> > > clk_core *core, {
> > > 
> > >  	lockdep_assert_held(&prepare_lock);
> > > 
> > > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > > +
> > > 
> > >  	if (!core) {
> > >  	
> > >  		req->rate = 0;
> > >  		return 0;
> > >  	
> > >  	}
> > > 
> > > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > > +
> > > 
> > >  	clk_core_init_rate_req(core, req);
> > > 
> > > -	if (clk_core_can_round(core))
> > > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > > +
> > > +	if (clk_core_can_round(core)) {
> > > +		pr_crit("%s +%d\n", __func__, __LINE__);
> > > 
> > >  		return clk_core_determine_round_nolock(core, req);
> > > 
> > > -	else if (core->flags & CLK_SET_RATE_PARENT)
> > > +	} else if (core->flags & CLK_SET_RATE_PARENT) {
> > > +		pr_crit("%s +%d\n", __func__, __LINE__);
> > > 
> > >  		return clk_core_round_rate_nolock(core->parent, req);
> > > 
> > > +	}
> > > 
> > >  	req->rate = core->rate;
> > >  	return 0;
> > > 
> > > @@ -2201,21 +2244,31 @@ static int clk_core_set_rate_nolock(struct
> > > clk_core
> > > *core, if (!core)
> > > 
> > >  		return 0;
> > > 
> > > +	pr_crit("%s: %s: rate %lu\n", __func__, core->name, req_rate);
> > > +
> > > 
> > >  	rate = clk_core_req_round_rate_nolock(core, req_rate);
> > > 
> > > +	pr_crit("%s: %s: rounded rate %lu\n", __func__, core->name,
> > 
> > req_rate);
> > 
> > > +
> > > 
> > >  	/* bail early if nothing to do */
> > >  	if (rate == clk_core_get_rate_nolock(core))
> > >  	
> > >  		return 0;
> > > 
> > > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > > +
> > > 
> > >  	/* fail on a direct rate set of a protected provider */
> > >  	if (clk_core_rate_is_protected(core))
> > >  	
> > >  		return -EBUSY;
> > > 
> > > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > > +
> > > 
> > >  	/* calculate new rates and get the topmost changed clock */
> > >  	top = clk_calc_new_rates(core, req_rate);
> > >  	if (!top)
> > >  	
> > >  		return -EINVAL;
> > > 
> > > +	pr_crit("%s +%d\n", __func__, __LINE__);
> > > +
> > > 
> > >  	ret = clk_pm_runtime_get(core);
> > >  	if (ret)
> > >  	
> > >  		return ret;
> > > 
> > > @@ -2367,6 +2420,16 @@ static int clk_set_rate_range_nolock(struct clk
> > > *clk, goto out;
> > > 
> > >  	}
> > > 
> > > +	pr_crit("%s: %s: orphan ? %c\n",
> > > +		__func__,
> > > +		clk->core->name,
> > > +		clk->core->orphan ? 'y' : 'n');
> > > +
> > > +	pr_crit("%s: %s: core req rate %lu\n",
> > > +		__func__,
> > > +		clk->core->name,
> > > +		clk->core->req_rate);
> > > +
> > > 
> > >  	/*
> > >  	
> > >  	 * Since the boundaries have been changed, let's give the
> > >  	 * opportunity to the provider to adjust the clock rate based on
> > > 
> > > @@ -2384,7 +2447,11 @@ static int clk_set_rate_range_nolock(struct clk
> > > *clk, * - the determine_rate() callback does not really check for
> > > 
> > >  	 *   this corner case when determining the rate
> > >  	 */
> > > 
> > > +
> > > 
> > >  	rate = clamp(clk->core->req_rate, min, max);
> > > 
> > > +
> > > +	pr_crit("%s: %s: clamped rate %lu\n", __func__, clk->core->name,
> > 
> > rate);
> > 
> > > +
> > > 
> > >  	ret = clk_core_set_rate_nolock(clk->core, rate);
> > >  	if (ret) {
> > >  	
> > >  		/* rollback the changes */
> > > 
> > > @@ -2599,6 +2666,8 @@ static int clk_core_set_parent_nolock(struct
> > > clk_core
> > > *core, } else {
> > > 
> > >  		__clk_recalc_rates(core, POST_RATE_CHANGE);
> > >  		__clk_recalc_accuracies(core);
> > > 
> > > +
> > > +		core->req_rate = core->rate;
> > > 
> > >  	}
> > >  
> > >  runtime_put:
> > > ---- >8 -----
> 
> So, let's try to follow this through:
> > Sure, here we go
> > ---
> > [    0.630873] Asymmetric key parser 'x509' registered
> > [    0.635802] Block layer SCSI generic (bsg) driver version 0.4 loaded
> > (major 243) [    0.643210] io scheduler mq-deadline registered
> > [    0.647758] io scheduler kyber registered
> > [    0.658708] clk_set_rate_range_nolock: arm_a53_div: orphan ? n
> > [    0.661717] clk_set_rate_range_nolock: arm_a53_div: core req rate
> > 800000000 [    0.668724] clk_set_rate_range_nolock: arm_a53_div: clamped
> > rate 800000000
> I'm assuming we hit the assigned-clock-parents in the clocks node, and
> we try to reparent arm_a53_div / IMX8MP_CLK_A53_SRC to sys_pll1_800m
> 
> I'm not entirely sure, but it looks like the arm_a53_div is a gate +
> divider, so that it has the same rate than its parent makes sens, and
> 800MHz for a CPU clock also makes sense.
> 
> It's also not an orphan, so it's likely to be a separate issue from Tony
> (and thus the fix doesn't help, sorry).
> 
> > [    0.675633] clk_core_set_rate_nolock: arm_a53_div: rate 800000000
> 
> Now, we set the rate to the same rate, this still makes sense.
> 
> > [    0.681761] clk_core_round_rate_nolock +1439
> > [    0.686048] clk_core_round_rate_nolock +1446
> > [    0.690333] clk_core_round_rate_nolock +1450
> > [    0.694619] clk_core_round_rate_nolock +1453
> > [    0.698908] clk_core_determine_round_nolock +1374 arm_a53_div
> 
> The clock has a round_rate / determine_rate implementation
> (clk_divider_round_rate, most likely), thus we call
> clk_core_determine_round_nolock()
> 
> > [    0.704681] clk_core_determine_round_nolock +1378
> > [    0.709408] clk_core_determine_round_nolock +1381
> > [    0.714133] clk_core_determine_round_nolock +1393
> 
> Still on the right path, we use clk_divider_determine_rate (too bad :)),
> it updates the rate
> 
> > [    0.718860] clk_core_set_rate_nolock: arm_a53_div: rounded rate
> > 800000000
> But it didn't change, good. The rounded clock hasn't changed,
> clk_core_set_rate_nolock returns, everything's great.
> 
> > [    0.725684] clk_set_rate_range_nolock: sys_pll1_800m: orphan ? n
> > [    0.731719] clk_set_rate_range_nolock: sys_pll1_800m: core req rate
> > 800000000 [    0.738894] clk_set_rate_range_nolock: sys_pll1_800m:
> > clamped rate 800000000 [    0.745983] clk_core_set_rate_nolock:
> > sys_pll1_800m: rate 800000000
> Then, __set_clk_parents calls clk_put() on the new parent,
> sys_pll1_800m, still not an orphan, still with a rate that makes sense.
> 
> > [    0.752281] clk_core_round_rate_nolock +1439
> > [    0.756569] clk_core_round_rate_nolock +1446
> > [    0.760862] clk_core_round_rate_nolock +1450
> > [    0.765152] clk_core_round_rate_nolock +1453
> > [    0.769435] clk_core_determine_round_nolock +1374 sys_pll1_800m
> 
> We still can round the rate, so we go to
> clk_core_determine_round_nolock()
> 
> > [    0.775385] clk_core_determine_round_nolock +1378
> > [    0.780114] clk_core_determine_round_nolock +1381
> > [    0.784833] clk_core_determine_round_nolock +1396
> 
> But this time using a round_rate implementation: clk_factor_round_rate
> (since sys_pll1_800m is a "pure" fixed factor clock). It has the flag
> CLK_SET_RATE_PARENT (set in imx_clk_hw_fixed_factor), so
> clk_factor_round_rate calls clk_hw_round_rate on its parent
> (sys_pll1_out) for the same rate since it has a factor of 1.
> 
> > [    0.789559] clk_core_round_rate_nolock +1439
> > [    0.793844] clk_core_round_rate_nolock +1446
> > [    0.798133] clk_core_round_rate_nolock +1450
> > [    0.802423] clk_core_round_rate_nolock +1456
> 
> We go through another round_rate cycle here, for sys_pll1_out. It can't
> modify the rate (since it's a gate) but it has CLK_SET_RATE_PARENT, so
> the rate rounding is forwarded to its parent: sys_pll1_bypass.
> 
> > [    0.806708] clk_core_round_rate_nolock +1439
> > [    0.810994] clk_core_round_rate_nolock +1446
> > [    0.815284] clk_core_round_rate_nolock +1450
> > [    0.819570] clk_core_round_rate_nolock +1453
> 
> We go through it, and call clk_core_determine_round_nolock again for
> sys_pll1_bypass.
> 
> > [    0.823856] clk_core_determine_round_nolock +1374 sys_pll1_bypass
> 
> Makes total sense so far.
> 
> > [    0.829981] clk_core_determine_round_nolock +1378
> > [    0.834706] clk_core_determine_round_nolock +1381
> > [    0.839431] clk_core_determine_round_nolock +1393
> > [    0.844159] clk_mux_determine_rate_flags: sys_pll1_bypass: requested
> > rate 800000000
> The requested rate does too. We still have our 800MHz.
> 
> > [    0.851856] clk_mux_determine_rate_flags: sys_pll1_bypass: current
> > parent sys_pll1 [    0.859471] clk_mux_determine_rate_flags:
> > sys_pll1_bypass: current parent rate 800000000
> sys_pll1_bypass has CLK_SET_RATE_NO_REPARENT (set by __imx_clk_hw_mux)
> and CLK_SET_RATE_PARENT (set by the driver when registering the clock),
> so clk_mux_determine_rate_flags will call __clk_determine_rate on its
> parent: sys_pll1. __clk_determine_rate then calls
> clk_core_round_rate_nolock.
> 
> > [    0.867608] clk_core_round_rate_nolock +1439
> > [    0.871894] clk_core_round_rate_nolock +1446
> > [    0.876182] clk_core_round_rate_nolock +1450
> > [    0.880477] clk_core_round_rate_nolock +1453
> 
> We call clk_core_determine_round_nolock on sys_pll1
> 
> > [    0.884758] clk_core_determine_round_nolock +1374 sys_pll1
> > [    0.890273] clk_core_determine_round_nolock +1378
> > [    0.894996] clk_core_determine_round_nolock +1381
> > [    0.899721] clk_core_determine_round_nolock +1396
> 
> sys_pll1 is a clk_pll14xx driver, it has a PLL_1416X type and a rate
> table, so it will use clk_pll1416x_ops. It has a round_rate
> implementation, clk_pll14xx_round_rate, that doesn't seem to be doing
> anything out of the ordinary. My assumption would be that it succeeds
> and returns a proper rate.
> 
> > [    0.904457] Unable to handle kernel NULL pointer dereference at virtual
> > address 0000000000000000
> > [    0.913285] Mem abort info:
> > [    0.916083]   ESR = 0x96000004
> > [    0.919147]   EC = 0x25: DABT (current EL), IL = 32 bits
> > [    0.924484]   SET = 0, FnV = 0
> > [    0.927547]   EA = 0, S1PTW = 0
> > [    0.930697]   FSC = 0x04: level 0 translation fault
> > [    0.935595] Data abort info:
> > [    0.938487]   ISV = 0, ISS = 0x00000004
> > [    0.942334]   CM = 0, WnR = 0
> > [    0.945304] [0000000000000000] user address but active_mm is swapper
> > [    0.951696] Internal error: Oops: 96000004 [#1] PREEMPT SMP
> > [    0.957292] Modules linked in:
> > [    0.960355] CPU: 2 PID: 1 Comm: swapper/0 Not tainted
> > 5.17.0-next-20220331+ #53 da834fe2485dc10e4c2f50265323ce628a30bc5e
> > [    0.971291] Hardware name: TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL
> > (DT) [    0.978292] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS
> > BTYPE=--) [    0.985291] pc : clk_mux_determine_rate_flags+0x33c/0x380
> > [    0.990714] lr : clk_mux_determine_rate_flags+0x10c/0x380
> > [    0.996141] sp : ffff800009ceb4a0
> > [    0.999464] x29: ffff800009ceb4a0 x28: ffff000002cf4700 x27:
> > 0000000000000001
> > [    1.006639] x26: ffff8000092fe728 x25: ffff800008eaa028 x24:
> > ffff800008ea95d8
> > [    1.013816] x23: ffff800008ea95d8 x22: ffff000002aab700 x21:
> > 000000002faf0800
> > [    1.020989] x20: ffff800009ceb640 x19: 0000000000000000 x18:
> > 0000000000004590
> > [    1.028164] x17: 617220746e657261 x16: 7020746e65727275 x15:
> > 63203a7373617079
> > [    1.035339] x14: 0000000000000000 x13: 363933312b206b63 x12:
> > 6f6c6f6e5f646e75
> > [    1.042514] x11: 6f725f656e696d72 x10: 657465645f65726f x9 :
> > 206b636f6c6f6e5f
> > [    1.049689] x8 : 646e756f725f656e x7 : 205d313237393938 x6 :
> > ffff800009a947c8
> > [    1.056864] x5 : ffff800008eb0310 x4 : 0000000000000009 x3 :
> > 000000002faf0800
> > [    1.064039] x2 : ffff800008eb039c x1 : ffff800008eaa028 x0 :
> > ffff8000092fd8b8
> > [    1.071217] Call trace:
> > [    1.073667]  clk_mux_determine_rate_flags+0x33c/0x380
> > [    1.078741]  clk_mux_determine_rate+0x10/0x20
> > [    1.083115]  clk_core_determine_round_nolock+0xd4/0x140
> > [    1.088364]  clk_core_round_rate_nolock+0xac/0xf8
> > [    1.093090]  clk_core_round_rate_nolock+0xd4/0xf8
> > [    1.097814]  clk_hw_round_rate+0x44/0x7c
> > [    1.101751]  clk_factor_round_rate+0x60/0x80
> > [    1.106041]  clk_core_determine_round_nolock+0x104/0x140
> > [    1.111376]  clk_core_round_rate_nolock+0xac/0xf8
> > [    1.116101]  clk_core_set_rate_nolock.part.0+0xac/0x21c
> > [    1.121351]  clk_set_rate_range_nolock+0x294/0x2b0
> 
> But then, where does this come from?
> 
> I'm not entirely sure, but the walk up the clock tree is sane to me.
> Could you run
> 
> ./scripts/faddr2line vmlinux 'clk_mux_determine_rate_flags+0x33c/0x380'
> 
> in your kernel compilation directory? (with ARCH and CROSS_COMPILE set
> if you're doing cross-compilation)?
> 
> My guess would be that we uncovered some other bug there, but I'm not
> sure what exactly.

Thanks for that lengthy analysis.

Here is the requested output:
---
$ ./scripts/faddr2line build_arm64/vmlinux 
'clk_mux_determine_rate_flags+0x33c/0x380'
clk_mux_determine_rate_flags+0x33c/0x380:
clk_mux_determine_rate_flags at drivers/clk/clk.c:627
---
From a first look it seems that 'best_parent' is just a NULL-pointer here.
With this small fix
--->8---
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 071857ef381a..45e081330fac 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -626,7 +626,7 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
 
        pr_crit("%s: Best parent %s (%lu)\n",
                __func__,
-               best_parent->name,
+               best_parent? best_parent->name : "unknown",
                best);
 
        return 0;
--->8---

The boot eventually get stuck, but at a later point.Which is probably why your 
analysis found nothing strange. Due to the size of the output I put it on a 
gist on github [1]. Please note that this is still based on a next-20220331 
based tree without the revert.

Best regards,
Alexander

[1] https://gist.github.com/tq-steina/f90c095d141575eaf75395f26671841a

Re: (EXT) Re: (EXT) Re: (EXT) Re: (EXT) Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

On Mon, Apr 04, 2022 at 09:06:42AM +0200, Alexander Stein wrote:
> Here is the requested output:
> ---
> $ ./scripts/faddr2line build_arm64/vmlinux 
> 'clk_mux_determine_rate_flags+0x33c/0x380'
> clk_mux_determine_rate_flags+0x33c/0x380:
> clk_mux_determine_rate_flags at drivers/clk/clk.c:627
> ---
> From a first look it seems that 'best_parent' is just a NULL-pointer here.
> With this small fix
> --->8---
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 071857ef381a..45e081330fac 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -626,7 +626,7 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
>  
>         pr_crit("%s: Best parent %s (%lu)\n",
>                 __func__,
> -               best_parent->name,
> +               best_parent? best_parent->name : "unknown",
>                 best);
>  
>         return 0;
> --->8---
> 
> The boot eventually get stuck, but at a later point.Which is probably why your 
> analysis found nothing strange. Due to the size of the output I put it on a 
> gist on github [1]. Please note that this is still based on a next-20220331 
> based tree without the revert.

I've looked into it over the weekend, and ran qemu on an imx6 to try to
see if it was any similar

I believe the issue comes from the fact that the core will forward rate
requests structure to the parent clock as is, and if the parent clock
changes the parent it wants, we end up trying to use that parent in the
initial clock which doesn't work really well.

I've fixed it in my branch here:
https://github.com/mripard/linux/commits/rpi/clk-improvements-more-fixes

Could you give it a try?
Maxime

Re: (EXT) Re: (EXT) Re: (EXT) Re: (EXT) Re: (EXT) Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Alexander Stein]

Hello Maxime,

Am Montag, 4. April 2022, 09:27:12 CEST schrieb Maxime Ripard:
> On Mon, Apr 04, 2022 at 09:06:42AM +0200, Alexander Stein wrote:
> > Here is the requested output:
> > ---
> > $ ./scripts/faddr2line build_arm64/vmlinux
> > 'clk_mux_determine_rate_flags+0x33c/0x380'
> > clk_mux_determine_rate_flags+0x33c/0x380:
> > clk_mux_determine_rate_flags at drivers/clk/clk.c:627
> > ---
> > From a first look it seems that 'best_parent' is just a NULL-pointer here.
> > With this small fix
> > --->8---
> > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > index 071857ef381a..45e081330fac 100644
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -626,7 +626,7 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
> > 
> >         pr_crit("%s: Best parent %s (%lu)\n",
> >         
> >                 __func__,
> > 
> > -               best_parent->name,
> > +               best_parent? best_parent->name : "unknown",
> > 
> >                 best);
> >         
> >         return 0;
> > 
> > --->8---
> > 
> > The boot eventually get stuck, but at a later point.Which is probably why
> > your analysis found nothing strange. Due to the size of the output I put
> > it on a gist on github [1]. Please note that this is still based on a
> > next-20220331 based tree without the revert.
> 
> I've looked into it over the weekend, and ran qemu on an imx6 to try to
> see if it was any similar
> 
> I believe the issue comes from the fact that the core will forward rate
> requests structure to the parent clock as is, and if the parent clock
> changes the parent it wants, we end up trying to use that parent in the
> initial clock which doesn't work really well.
> 
> I've fixed it in my branch here:
> https://github.com/mripard/linux/commits/rpi/clk-improvements-more-fixes

Thanks for providing another patchset. Unfortunately, my board hangs still at 
the same location. For reference I put a branch based on next-20220401 on [1].
Reverting still does the jobs, a branch is shown on [2]

next-20220404 has the offending patch already reverted, so this should work 
again, I did not test it on that base on purpose.

Best regards,
Alexander

[1] https://github.com/tq-steina/linux/tree/clk-fix
[2] https://github.com/tq-steina/linux/tree/clk-revert

Re: (EXT) Re: (EXT) Re: (EXT) Re: (EXT) Re: (EXT) Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2543 bytes --]

Hi Alexander,

On Mon, Apr 04, 2022 at 12:54:02PM +0200, Alexander Stein wrote:
> Am Montag, 4. April 2022, 09:27:12 CEST schrieb Maxime Ripard:
> > On Mon, Apr 04, 2022 at 09:06:42AM +0200, Alexander Stein wrote:
> > > Here is the requested output:
> > > ---
> > > $ ./scripts/faddr2line build_arm64/vmlinux
> > > 'clk_mux_determine_rate_flags+0x33c/0x380'
> > > clk_mux_determine_rate_flags+0x33c/0x380:
> > > clk_mux_determine_rate_flags at drivers/clk/clk.c:627
> > > ---
> > > From a first look it seems that 'best_parent' is just a NULL-pointer here.
> > > With this small fix
> > > --->8---
> > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> > > index 071857ef381a..45e081330fac 100644
> > > --- a/drivers/clk/clk.c
> > > +++ b/drivers/clk/clk.c
> > > @@ -626,7 +626,7 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
> > > 
> > >         pr_crit("%s: Best parent %s (%lu)\n",
> > >         
> > >                 __func__,
> > > 
> > > -               best_parent->name,
> > > +               best_parent? best_parent->name : "unknown",
> > > 
> > >                 best);
> > >         
> > >         return 0;
> > > 
> > > --->8---
> > > 
> > > The boot eventually get stuck, but at a later point.Which is probably why
> > > your analysis found nothing strange. Due to the size of the output I put
> > > it on a gist on github [1]. Please note that this is still based on a
> > > next-20220331 based tree without the revert.
> > 
> > I've looked into it over the weekend, and ran qemu on an imx6 to try to
> > see if it was any similar
> > 
> > I believe the issue comes from the fact that the core will forward rate
> > requests structure to the parent clock as is, and if the parent clock
> > changes the parent it wants, we end up trying to use that parent in the
> > initial clock which doesn't work really well.
> > 
> > I've fixed it in my branch here:
> > https://github.com/mripard/linux/commits/rpi/clk-improvements-more-fixes
> 
> Thanks for providing another patchset. Unfortunately, my board hangs still at 
> the same location. For reference I put a branch based on next-20220401 on [1].
> Reverting still does the jobs, a branch is shown on [2]
> 
> next-20220404 has the offending patch already reverted, so this should work 
> again, I did not test it on that base on purpose.

Could you give it another try with the branch I pushed today?

I've fixed some issues for exynos4 that could explain why it doesn't
boot on imx8 as well.

Maxime

[-- Attachment #2: signature.asc --]
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Re: (EXT) Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 20616 bytes --]

Hi Alexandre, Tony, Mareek, Naresh,

On Fri, Apr 01, 2022 at 02:27:36PM +0200, Maxime Ripard wrote:
> On Fri, Apr 01, 2022 at 01:55:20PM +0200, Alexander Stein wrote:
> > Am Donnerstag, 31. März 2022, 17:31:34 CEST schrieb Maxime Ripard:
> > > * PGP Signed by an unknown key
> > > 
> > > Hi Tony,
> > > 
> > > On Thu, Mar 31, 2022 at 06:00:42PM +0300, Tony Lindgren wrote:
> > > > * Maxime Ripard <maxime@cerno.tech> [220331 09:52]:
> > > > > On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> > > > > > It seems the dts assigned-clock-parents no longer works now?
> > > > > 
> > > > > That would make some kind of sense, __set_clk_parents calls clk_put on
> > > > > both the assigned clock and its parent.
> > > > > 
> > > > > Could you see what parent (and why?) it tries to enforce then?
> > > > 
> > > > It picks the other option available for the mux clock that only has
> > > > two options. No idea why, but if you have some debug patch in mind I
> > > > can give it a try.
> > > > 
> > > > > It looks like the gpt1_fck driver might favor another parent for that
> > > > > rate, which, if it's an invalid configuration, shouldn't really happen?
> > > > 
> > > > Hmm there's a gate clock and a mux clock, there's not really a rate
> > > > selection available here for the sources.
> > > 
> > > If I followed the OMAP driver properly, clk_mux_determine_rate_flags is
> > > doing the heavy lifting, could you run your test with
> > 
> > I'm affected by this patch as well on an imx8mp platform (see [1] for some 
> > details)
> > 
> > In the failing case with with your patch applied I get the following error 
> > ---
> > [    0.661064] clk_set_rate_range_nolock: core req rate 500000000                                                                    
> > [    0.664084] clk_set_rate_range_nolock: clamped rate 500000000                                                                     
> > [    0.669851] clk_core_set_rate_nolock: rate 500000000                                                                              
> > [    0.674843] clk_core_set_rate_nolock: rounded rate 500000000                                                                      
> > [    0.680536] clk_set_rate_range_nolock: core req rate 800000000                                                                    
> > [    0.686389] clk_set_rate_range_nolock: clamped rate 800000000                                                                     
> > [    0.692164] clk_core_set_rate_nolock: rate 800000000                                                                              
> > [    0.697153] clk_mux_determine_rate_flags: requested rate 800000000                                                                
> > [    0.703363] clk_mux_determine_rate_flags: current parent sys_pll1                                                                 
> > [    0.709487] clk_mux_determine_rate_flags: current parent rate 800000000                                                           
> > [    0.716147] Unable to handle kernel NULL pointer dereference at virtual 
> > address 0000000000000000
> > [    0.724977] Mem abort info:                                                                                                       
> > [    0.727775]   ESR = 0x96000004                                                                                                    
> > [    0.730835]   EC = 0x25: DABT (current EL), IL = 32 bits                                                                          
> > [    0.736177]   SET = 0, FnV = 0                                                                                                    
> > [    0.739239]   EA = 0, S1PTW = 0                                                                                                   
> > [    0.742382]   FSC = 0x04: level 0 translation fault                                                                               
> > [    0.747287] Data abort info:                                                                                                      
> > [    0.750172]   ISV = 0, ISS = 0x00000004                                                                                           
> > [    0.754027]   CM = 0, WnR = 0                                                                                                     
> > [    0.757002] [0000000000000000] user address but active_mm is swapper                                                              
> > [    0.763394] Internal error: Oops: 96000004 [#1] PREEMPT SMP                                                                       
> > [    0.768985] Modules linked in:                                                                                                    
> > [    0.772049] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.17.0-next-20220331+ 
> > #48 8e9d24095c7f6b15f85bc2ad57a5609e219130b9          
> > [    0.782984] Hardware name: TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL (DT)                                                       
> > [    0.789985] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)                                                       
> > [    0.796985] pc : clk_mux_determine_rate_flags+0x280/0x2cc                                                                         
> > [    0.802407] lr : clk_mux_determine_rate_flags+0xf4/0x2cc                                                                          
> > [    0.807747] sp : ffff800009ceb590                                                                                                 
> > [    0.811072] x29: ffff800009ceb590 x28: ffff800009ceb6a0 x27: 
> > ffff800008eaa038                                                     
> > [    0.818245] x26: ffff8000092fe0b0 x25: ffff000000090000 x24: 
> > ffff000000090000                                                     
> > [    0.825420] x23: 0000000000000000 x22: ffff800008ea95d8 x21: 
> > ffff0000028f4700                                                     
> > [    0.832595] x20: 000000002faf0800 x19: 0000000000000000 x18: 
> > 0000000000004590                                                     
> > [    0.839770] x17: 0000000000004570 x16: 0000000000004560 x15: 
> > ffff8000092ff250                                                     
> > [    0.846945] x14: 0000000000000000 x13: 3030303030303030 x12: 
> > 3820657461722074                                                     
> > [    0.854120] x11: 6e6572617020746e x10: 6572727563203a73 x9 : 
> > 7563203a7367616c                                                     
> > [    0.861295] x8 : 665f657461725f65 x7 : 205d373834393037 x6 : 
> > ffff800009a947c8                                                     
> > [    0.868472] x5 : ffff800008eafe68 x4 : 0000000000000009 x3 : 
> > 000000002faf0800                                                     
> > [    0.875645] x2 : ffff800008eafef4 x1 : ffff800008eaa038 x0 : 
> > ffff8000092fd5b8                                                     
> > [    0.882822] Call trace:                                                                                                           
> > [    0.885273]  clk_mux_determine_rate_flags+0x280/0x2cc                                                                             
> > [    0.890347]  clk_mux_determine_rate+0x10/0x20                                                                                     
> > [    0.894720]  clk_core_determine_round_nolock+0x4c/0xb4                                                                            
> > [    0.899882]  clk_core_round_rate_nolock+0x30/0x80                                                                                 
> > [    0.904607]  clk_core_round_rate_nolock+0x70/0x80                                                                                 
> > [    0.909334]  clk_hw_round_rate+0x44/0x74                                                                                          
> > [    0.913270]  clk_factor_round_rate+0x60/0x80                                                                                      
> > [    0.917557]  clk_core_determine_round_nolock+0x88/0xb4                                                                            
> > [    0.922720]  clk_core_round_rate_nolock+0x30/0x80                                                                                 
> > [    0.927445]  clk_core_set_rate_nolock.part.0+0xa4/0x1d0                                                                           
> > [    0.932695]  clk_set_rate_range_nolock+0x234/0x244                                                                                
> > [    0.937507]  __clk_put+0x60/0x12c                                                                                                 
> > [    0.940834]  clk_put+0xc/0x1c                                                                                                     
> > [    0.943809]  __set_clk_parents+0x12c/0x244                                                                                        
> > [    0.947920]  of_clk_set_defaults+0x20/0x50                                                                                        
> > [    0.952032]  of_clk_add_hw_provider.part.0+0x94/0x120                                                                             
> > [    0.957107]  of_clk_add_hw_provider+0x10/0x20                                                                                     
> > [    0.961482]  imx8mp_clocks_probe+0x3458/0x34d0                                                                                    
> > [    0.965945]  platform_probe+0x64/0x100                                                                                            
> > [    0.969707]  call_driver_probe+0x28/0x130                                                                                         
> > [    0.973732]  really_probe+0x178/0x310                                                                                             
> > [    0.977409]  __driver_probe_device+0xfc/0x144                                                                                     
> > [    0.981782]  driver_probe_device+0x38/0x12c                                                                                       
> > [    0.985982]  __driver_attach+0xcc/0x220                                                                                           
> > [    0.989834]  bus_for_each_dev+0x6c/0xc0                                                                                           
> > [    0.993682]  driver_attach+0x20/0x2c                                                                                              
> > [    0.997270]  bus_add_driver+0x140/0x230                                                                                           
> > [    1.001120]  driver_register+0x74/0x120                                                                                           
> > [    1.004970]  __platform_driver_register+0x24/0x30                                                                                 
> > [    1.009697]  imx8mp_clk_driver_init+0x18/0x20                                                                                     
> > [    1.014070]  do_one_initcall+0x58/0x200                                                                                           
> > [    1.017920]  do_initcalls+0x164/0x19c                                                                                             
> > [    1.021597]  kernel_init_freeable+0x134/0x17c                                                                                     
> > [    1.025970]  kernel_init+0x2c/0x150                                                                                               
> > [    1.029470]  ret_from_fork+0x10/0x20                                                                                              
> > [    1.033065] Code: f9000f94 912982c1 b0002900 9116e000 (f9400262)                                                                  
> > [    1.039188] ---[ end trace 0000000000000000 ]---                                                                                  
> > [    1.043869] Kernel panic - not syncing: Attempted to kill init! 
> > exitcode=0x0000000b                                               
> > [    1.051523] SMP: stopping secondary CPUs                                                                                          
> > [    1.055467] Kernel Offset: disabled                                                                                               
> > [    1.058960] CPU features: 0x000,00020009,00001082                                                                                 
> > [    1.063684] Memory Limit: none                                                                                                    
> > [    1.066748] ---[ end Kernel panic - not syncing: Attempted to kill init! 
> > exitcode=0x0000000b ]---
> > ---
> > 
> > With the $subject patch reverted and bootable system:
> > ---
> > [    0.659922] clk_core_set_rate_nolock: rate 1000000000                                                                             
> > [    0.662154] clk_core_set_rate_nolock: rounded rate 1000000000                                                                     
> > [    0.667932] clk_core_set_rate_nolock: rate 800000000                                                                              
> > [    0.672918] clk_core_set_rate_nolock: rounded rate 800000000                                                                      
> > [    0.678601] clk_core_set_rate_nolock: rate 500000000                                                                              
> > [    0.683592] clk_core_set_rate_nolock: rounded rate 500000000                                                                      
> > [    0.689276] clk_core_set_rate_nolock: rate 400000000                                                                              
> > [    0.694267] clk_core_set_rate_nolock: rounded rate 400000000                                                                      
> > [    0.699980] clk_core_set_rate_nolock: rate 800000000                                                                              
> > [    0.704942] clk_core_set_rate_nolock: rounded rate 800000000                                                                      
> > [    0.710627] clk_core_set_rate_nolock: rate 393216000                                                                              
> > [    0.715611] clk_core_set_rate_nolock: rounded rate 393216000                                                                      
> > [    0.721815] clk_core_set_rate_nolock: rate 361267200                                                                              
> > [    0.726284] clk_core_set_rate_nolock: rounded rate 361267200                                                                      
> > [    0.734097] clk_core_set_rate_nolock: rate 800000000                                                                              
> > [    0.736977] clk_core_set_rate_nolock: rounded rate 800000000                                                                      
> > [    0.742652] clk_core_set_rate_nolock: rate 400000000                                                                              
> > [    0.747645] clk_core_set_rate_nolock: rounded rate 400000000                                                                      
> > [    0.754565] clk_core_set_rate_nolock: rate 500000000                                                                              
> > [    0.758331] clk_core_set_rate_nolock: rounded rate 500000000                                                                      
> > [    0.764688] SoC: i.MX8MP revision 1.1                                                                                             
> > [    0.767931] clk_core_set_rate_nolock: rate 500000000                                                                              
> > [    0.772675] clk_core_set_rate_nolock: rounded rate 500000000                                                                      
> > [    0.778354] clk_core_set_rate_nolock: rate 200000000                                                                              
> > [    0.783351] clk_core_set_rate_nolock: rounded rate 200000000                                                                      
> > [    0.793748] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled                                                               
> > [    0.798952] 30860000.serial: ttymxc0 at MMIO 0x30860000 (irq = 34, 
> > base_baud = 5000000) is a IMX                                  
> > [    0.806527] 30880000.serial: ttymxc2 at MMIO 0x30880000 (irq = 35, 
> > base_baud = 5000000) is a IMX                                  
> > [    0.815329] 30890000.serial: ttymxc1 at MMIO 0x30890000 (irq = 36, 
> > base_baud = 5000000) is a IMX                                  
> > [    0.824176] 30a60000.serial: ttymxc3 at MMIO 0x30a60000 (irq = 43, 
> > base_baud = 1500000) is a IMX                                  
> > [    0.832588] printk: console [ttymxc3] enabled                                                                                     
> > [    0.832588] printk: console [ttymxc3] enabled                                                                                     
> > [    0.841244] printk: bootconsole [ec_imx6q0] disabled                                                                              
> > [    0.841244] printk: bootconsole [ec_imx6q0] disabled                                                                              
> > [    0.857871] clk_core_set_rate_nolock: rate 80000000                                                                               
> > [    0.862796] clk_core_set_rate_nolock: rounded rate 80000000                                                                       
> > [    0.868469] clk_core_set_rate_nolock: rate 20000000                                                                               
> > [    0.873364] clk_core_set_rate_nolock: rounded rate 20000000                                                                       
> > [    0.879258] clk_core_set_rate_nolock: rate 80000000                                                                               
> > [    0.884154] clk_core_set_rate_nolock: rounded rate 80000000
> > [...]
> > ---
> > 
> > The 500000000 and 800000000 look a bit like the assigned-clock-rates for 
> > clock-controller@30380000 in arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > 
> > If you need some more information, do not hesitate to ask
> 
> Thanks a lot to you three for all your testing. I think I know what
> might be going on:
> 
> We use the last requested rate on clk_set_rate_range
> (clk_core.req_rate), and that requested rate if the clock is orphan will
> be set to 0, so if we were to call clk_set_rate_range before the parent
> clock is registered, we would effectively call a clk_set_rate to 0
> 
> And the assigned-clocks stuff is handled by __set_clk_parents and
> __set_clk_rates, called by of_clk_set_defaults(), in turn called by
> of_clk_init and of_clk_add_provider. Both __set_clk_parents and
> __set_clk_rates will call clk_put once done with the clock, and we will
> with this patch trigger the clk_set_rate to 0 I mentioned before.
> 
> So we just became very good at triggering the underlying issue :)
> 
> And I think it's that while we update the requested rate when the
> missing parent is registered, we never do when we mux away from it using
> clk_set_parent.

I've worked on a similar setup than Alexander today using qemu and
figured out a fairly significant bug in the rate setting logic in the
clock framework, that could explain why OMAP is going crazy as well.

I've pushed a branch here with multiple fixes:
https://github.com/mripard/linux/tree/rpi/clk-improvements-more-fixes

Let me know if it fixes your issues.

If it doesn't, could you point me to a setup (using qemu?) that could
reproduce this issue, or alternatively to a cheap, available, board I
could buy to debug this further?

Thanks!
Maxime

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Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

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Hi Tony,

On Thu, Mar 31, 2022 at 12:42:10PM +0300, Tony Lindgren wrote:
> * Maxime Ripard <maxime@cerno.tech> [700101 02:00]:
> > Hi Marek,
> > 
> > On Wed, Mar 30, 2022 at 10:06:13AM +0200, Marek Szyprowski wrote:
> > > On 25.03.2022 17:11, Maxime Ripard wrote:
> > > > While the current code will trigger a new clk_set_rate call whenever the
> > > > rate boundaries are changed through clk_set_rate_range, this doesn't
> > > > occur when clk_put() is called.
> > > >
> > > > However, this is essentially equivalent since, after clk_put()
> > > > completes, those boundaries won't be enforced anymore.
> > > >
> > > > Let's add a call to clk_set_rate_range in clk_put to make sure those
> > > > rate boundaries are dropped and the clock drivers can react.
> > > >
> > > > Let's also add a few tests to make sure this case is covered.
> > > >
> > > > Fixes: c80ac50cbb37 ("clk: Always set the rate on clk_set_range_rate")
> > > > Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> > > 
> > > This patch landed recently in linux-next 20220328 as commit 7dabfa2bc480 
> > > ("clk: Drop the rate range on clk_put()"). Sadly it breaks booting of 
> > > the few of my test systems: Samsung ARM 32bit Exynos3250 based Rinato 
> > > board and all Amlogic Meson G12B/SM1 based boards (Odroid C4, N2, Khadas 
> > > VIM3/VIM3l). Rinato hangs always with the following oops:
> > > 
> > > --->8---
> > > 
> > > Kernel panic - not syncing: MCT hangs after writing 4 (offset:0x420)
> > > CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.17.0-rc1-00014-g7dabfa2bc480 
> > > #11551
> > > Hardware name: Samsung Exynos (Flattened Device Tree)
> > >   unwind_backtrace from show_stack+0x10/0x14
> > >   show_stack from dump_stack_lvl+0x58/0x70
> > >   dump_stack_lvl from panic+0x10c/0x328
> > >   panic from exynos4_mct_tick_stop+0x0/0x2c
> > > ---[ end Kernel panic - not syncing: MCT hangs after writing 4 
> > > (offset:0x420) ]---
> > > 
> > > --->8---
> > > 
> > > Amlogic boards hang randomly during early userspace init, usually just 
> > > after loading the driver modules.
> > > 
> > > Reverting $subject on top of linux-next fixes all those problems.
> > > 
> > > I will try to analyze it a bit more and if possible provide some more 
> > > useful/meaning full logs later.
> > 
> > I'm not sure what could go wrong there, but if you can figure out the
> > clock, if it tries to set a new rate and what rate it is, it would be
> > awesome :)
> 
> I'm also seeing clockevent break on omaps as a wrong source clock gets
> picked.
> 
> It seems the dts assigned-clock-parents no longer works now?
> 
> So the following no longer sets omap_32k_fck as the clockevent source:
> 
> timer@0 {
> 	assigned-clocks = <&gpt1_fck>;
> 	assigned-clock-parents = <&omap_32k_fck>;
> };

I haven't been able to find an omap3 board or a qemu target that could
help me debug this, but I fixed a few issues already that could fix omap
as well.

Could you test today's
https://github.com/mripard/linux/tree/rpi/clk-improvements-more-fixes

And let me know if it works?

Thanks!
Maxime

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Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Tony Lindgren]

Hi,

* Maxime Ripard <maxime@cerno.tech> [220407 07:51]:
> I haven't been able to find an omap3 board or a qemu target that could
> help me debug this, but I fixed a few issues already that could fix omap
> as well.
> 
> Could you test today's
> https://github.com/mripard/linux/tree/rpi/clk-improvements-more-fixes
> 
> And let me know if it works?

Yes sorry I've been meaning to try your fixes but had some file system
issues on my build box after a power cut while updating the system. All
good now though, I should be able to give it a try this afternoon.

Regards,

Tony

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [220407 08:23]:
> Hi,
> 
> * Maxime Ripard <maxime@cerno.tech> [220407 07:51]:
> > I haven't been able to find an omap3 board or a qemu target that could
> > help me debug this, but I fixed a few issues already that could fix omap
> > as well.
> > 
> > Could you test today's
> > https://github.com/mripard/linux/tree/rpi/clk-improvements-more-fixes
> > 
> > And let me know if it works?
> 
> Yes sorry I've been meaning to try your fixes but had some file system
> issues on my build box after a power cut while updating the system. All
> good now though, I should be able to give it a try this afternoon.

It now boots, but does a lot of checks on the clocks before the timers
get initialized compared to v5.18-rc1. And then there's this:

[    2.532501] clk_core_set_rate_nolock +2293: ssi_ssr_fck_3430es2 affected!
...
[    2.554443]  unwind_backtrace from show_stack+0x10/0x14
[    2.559875]  show_stack from dump_stack_lvl+0x40/0x4c
[    2.565093]  dump_stack_lvl from clk_core_set_rate_nolock+0x278/0x2c4
[    2.571777]  clk_core_set_rate_nolock from clk_set_rate_range_nolock.part.0+0x154/0x384
[    2.580047]  clk_set_rate_range_nolock.part.0 from __clk_put+0x64/0x174
[    2.586853]  __clk_put from clk_add_alias+0x48/0x5c
[    2.591918]  clk_add_alias from _add_clkdev.part.0+0x94/0x154
[    2.597869]  _add_clkdev.part.0 from omap_device_alloc+0x88/0x114
[    2.604156]  omap_device_alloc from _omap_device_notifier_call+0x25c/0x3b4
[    2.611236]  _omap_device_notifier_call from blocking_notifier_call_chain+0x6c/0x90
[    2.619140]  blocking_notifier_call_chain from device_add+0x360/0x894
[    2.625823]  device_add from of_platform_device_create_pdata+0x8c/0xb8
[    2.632568]  of_platform_device_create_pdata from of_platform_bus_create+0x194/0x22c
[    2.640563]  of_platform_bus_create from of_platform_bus_create+0x1e0/0x22c
[    2.647735]  of_platform_bus_create from of_platform_populate+0x60/0xb8
[    2.654571]  of_platform_populate from pdata_quirks_init+0xb4/0xe0
[    2.660980]  pdata_quirks_init from omap_generic_init+0xc/0x18
[    2.666992]  omap_generic_init from customize_machine+0x1c/0x30
[    2.673126]  customize_machine from do_one_initcall+0x44/0x24c
[    2.679138]  do_one_initcall from kernel_init_freeable+0x1e8/0x298
[    2.685546]  kernel_init_freeable from kernel_init+0x14/0x140
[    2.691467]  kernel_init from ret_from_fork+0x14/0x24

I'll email you the full log separately to look at.

Regards,

Tony

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

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Hi Tony,

On Thu, Apr 07, 2022 at 02:08:05PM +0300, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [220407 08:23]:
> > Hi,
> > 
> > * Maxime Ripard <maxime@cerno.tech> [220407 07:51]:
> > > I haven't been able to find an omap3 board or a qemu target that could
> > > help me debug this, but I fixed a few issues already that could fix omap
> > > as well.
> > > 
> > > Could you test today's
> > > https://github.com/mripard/linux/tree/rpi/clk-improvements-more-fixes
> > > 
> > > And let me know if it works?
> > 
> > Yes sorry I've been meaning to try your fixes but had some file system
> > issues on my build box after a power cut while updating the system. All
> > good now though, I should be able to give it a try this afternoon.
> 
> It now boots, but does a lot of checks on the clocks before the timers
> get initialized compared to v5.18-rc1.

I was about to say that this is fairly normal with the new behaviour,
but I've reworked the initial patch in that discussion to only call into
clk_set_rate_range if there was a range on that clock to begin with.

It should remove the huge majority of the checks you mentioned (and
hopefully get rid of most of the side effects as well).

It's now pushed to my branch, so it would be awesome if you could test
again.

> And then there's this:
> 
> [    2.532501] clk_core_set_rate_nolock +2293: ssi_ssr_fck_3430es2 affected!
> ...
> [    2.554443]  unwind_backtrace from show_stack+0x10/0x14
> [    2.559875]  show_stack from dump_stack_lvl+0x40/0x4c
> [    2.565093]  dump_stack_lvl from clk_core_set_rate_nolock+0x278/0x2c4
> [    2.571777]  clk_core_set_rate_nolock from clk_set_rate_range_nolock.part.0+0x154/0x384
> [    2.580047]  clk_set_rate_range_nolock.part.0 from __clk_put+0x64/0x174
> [    2.586853]  __clk_put from clk_add_alias+0x48/0x5c
> [    2.591918]  clk_add_alias from _add_clkdev.part.0+0x94/0x154
> [    2.597869]  _add_clkdev.part.0 from omap_device_alloc+0x88/0x114
> [    2.604156]  omap_device_alloc from _omap_device_notifier_call+0x25c/0x3b4
> [    2.611236]  _omap_device_notifier_call from blocking_notifier_call_chain+0x6c/0x90
> [    2.619140]  blocking_notifier_call_chain from device_add+0x360/0x894
> [    2.625823]  device_add from of_platform_device_create_pdata+0x8c/0xb8
> [    2.632568]  of_platform_device_create_pdata from of_platform_bus_create+0x194/0x22c
> [    2.640563]  of_platform_bus_create from of_platform_bus_create+0x1e0/0x22c
> [    2.647735]  of_platform_bus_create from of_platform_populate+0x60/0xb8
> [    2.654571]  of_platform_populate from pdata_quirks_init+0xb4/0xe0
> [    2.660980]  pdata_quirks_init from omap_generic_init+0xc/0x18
> [    2.666992]  omap_generic_init from customize_machine+0x1c/0x30
> [    2.673126]  customize_machine from do_one_initcall+0x44/0x24c
> [    2.679138]  do_one_initcall from kernel_init_freeable+0x1e8/0x298
> [    2.685546]  kernel_init_freeable from kernel_init+0x14/0x140
> [    2.691467]  kernel_init from ret_from_fork+0x14/0x24

It shouldn't be there anymore after that rework, but I couldn't find
wher the ssi_ssr_fck clock was defined? The only relevant driver seems
to be omap_ssi_core.c but I don't see any clock driver registered there
either.

Thanks!
Maxime

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Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Tony Lindgren]

* Maxime Ripard <maxime@cerno.tech> [220407 13:43]:
> On Thu, Apr 07, 2022 at 02:08:05PM +0300, Tony Lindgren wrote:
> > It now boots, but does a lot of checks on the clocks before the timers
> > get initialized compared to v5.18-rc1.
> 
> I was about to say that this is fairly normal with the new behaviour,
> but I've reworked the initial patch in that discussion to only call into
> clk_set_rate_range if there was a range on that clock to begin with.
> 
> It should remove the huge majority of the checks you mentioned (and
> hopefully get rid of most of the side effects as well).

OK yeah thanks, looks good to me now. Boot time looks normal, timer clocks
are right, and runtime PM still works too.

> It shouldn't be there anymore after that rework, but I couldn't find
> wher the ssi_ssr_fck clock was defined? The only relevant driver seems
> to be omap_ssi_core.c but I don't see any clock driver registered there
> either.

I'm not seeing this warning any longer :)

FYI, this clock is defined here:

$ git grep ssi_ssr_fck_3430es2
arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi: ssi_ssr_fck: ssi_ssr_fck_3430es2 {
drivers/clk/ti/clk-3xxx.c:      DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),

Yeah it's confusing, the clock is still created based on the node name.
I have some clean-up patches coming to fix most of the related make dtbs
checks warnings now that the clock driver changes got merged.

Regards,

Tony

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Marek Szyprowski]

Hi,

On 30.03.2022 10:47, Maxime Ripard wrote:
> On Wed, Mar 30, 2022 at 10:06:13AM +0200, Marek Szyprowski wrote:
>> On 25.03.2022 17:11, Maxime Ripard wrote:
>>> While the current code will trigger a new clk_set_rate call whenever the
>>> rate boundaries are changed through clk_set_rate_range, this doesn't
>>> occur when clk_put() is called.
>>>
>>> However, this is essentially equivalent since, after clk_put()
>>> completes, those boundaries won't be enforced anymore.
>>>
>>> Let's add a call to clk_set_rate_range in clk_put to make sure those
>>> rate boundaries are dropped and the clock drivers can react.
>>>
>>> Let's also add a few tests to make sure this case is covered.
>>>
>>> Fixes: c80ac50cbb37 ("clk: Always set the rate on clk_set_range_rate")
>>> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
>> This patch landed recently in linux-next 20220328 as commit 7dabfa2bc480
>> ("clk: Drop the rate range on clk_put()"). Sadly it breaks booting of
>> the few of my test systems: Samsung ARM 32bit Exynos3250 based Rinato
>> board and all Amlogic Meson G12B/SM1 based boards (Odroid C4, N2, Khadas
>> VIM3/VIM3l). Rinato hangs always with the following oops:
>>
>> --->8---
>>
>> Kernel panic - not syncing: MCT hangs after writing 4 (offset:0x420)
>> CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.17.0-rc1-00014-g7dabfa2bc480
>> #11551
>> Hardware name: Samsung Exynos (Flattened Device Tree)
>>    unwind_backtrace from show_stack+0x10/0x14
>>    show_stack from dump_stack_lvl+0x58/0x70
>>    dump_stack_lvl from panic+0x10c/0x328
>>    panic from exynos4_mct_tick_stop+0x0/0x2c
>> ---[ end Kernel panic - not syncing: MCT hangs after writing 4
>> (offset:0x420) ]---
>>
>> --->8---
>>
>> Amlogic boards hang randomly during early userspace init, usually just
>> after loading the driver modules.
>>
>> Reverting $subject on top of linux-next fixes all those problems.
>>
>> I will try to analyze it a bit more and if possible provide some more
>> useful/meaning full logs later.
> I'm not sure what could go wrong there, but if you can figure out the
> clock, if it tries to set a new rate and what rate it is, it would be
> awesome :)

So far I've noticed that the problem is caused by setting rate of some 
clocks to zero. The following patch fixes my issues:

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 32a9eaf35c6b..39cab08dbecb 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2201,6 +2201,9 @@ static int clk_core_set_rate_nolock(struct 
clk_core *core,
         if (!core)
                 return 0;

+       if (req_rate == 0)
+               return 0;
+
         rate = clk_core_req_round_rate_nolock(core, req_rate);

         /* bail early if nothing to do */
--

I will soon grab the call stack and relevant clock topology show how the 
rate is set to zero.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH v2 3/3] clk: Drop the rate range on clk_put

[Maxime Ripard]

On Thu, Mar 31, 2022 at 11:56:51AM +0200, Marek Szyprowski wrote:
> Hi,
> 
> On 30.03.2022 10:47, Maxime Ripard wrote:
> > On Wed, Mar 30, 2022 at 10:06:13AM +0200, Marek Szyprowski wrote:
> >> On 25.03.2022 17:11, Maxime Ripard wrote:
> >>> While the current code will trigger a new clk_set_rate call whenever the
> >>> rate boundaries are changed through clk_set_rate_range, this doesn't
> >>> occur when clk_put() is called.
> >>>
> >>> However, this is essentially equivalent since, after clk_put()
> >>> completes, those boundaries won't be enforced anymore.
> >>>
> >>> Let's add a call to clk_set_rate_range in clk_put to make sure those
> >>> rate boundaries are dropped and the clock drivers can react.
> >>>
> >>> Let's also add a few tests to make sure this case is covered.
> >>>
> >>> Fixes: c80ac50cbb37 ("clk: Always set the rate on clk_set_range_rate")
> >>> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> >> This patch landed recently in linux-next 20220328 as commit 7dabfa2bc480
> >> ("clk: Drop the rate range on clk_put()"). Sadly it breaks booting of
> >> the few of my test systems: Samsung ARM 32bit Exynos3250 based Rinato
> >> board and all Amlogic Meson G12B/SM1 based boards (Odroid C4, N2, Khadas
> >> VIM3/VIM3l). Rinato hangs always with the following oops:
> >>
> >> --->8---
> >>
> >> Kernel panic - not syncing: MCT hangs after writing 4 (offset:0x420)
> >> CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.17.0-rc1-00014-g7dabfa2bc480
> >> #11551
> >> Hardware name: Samsung Exynos (Flattened Device Tree)
> >>    unwind_backtrace from show_stack+0x10/0x14
> >>    show_stack from dump_stack_lvl+0x58/0x70
> >>    dump_stack_lvl from panic+0x10c/0x328
> >>    panic from exynos4_mct_tick_stop+0x0/0x2c
> >> ---[ end Kernel panic - not syncing: MCT hangs after writing 4
> >> (offset:0x420) ]---
> >>
> >> --->8---
> >>
> >> Amlogic boards hang randomly during early userspace init, usually just
> >> after loading the driver modules.
> >>
> >> Reverting $subject on top of linux-next fixes all those problems.
> >>
> >> I will try to analyze it a bit more and if possible provide some more
> >> useful/meaning full logs later.
> > I'm not sure what could go wrong there, but if you can figure out the
> > clock, if it tries to set a new rate and what rate it is, it would be
> > awesome :)
> 
> So far I've noticed that the problem is caused by setting rate of some 
> clocks to zero. The following patch fixes my issues:
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 32a9eaf35c6b..39cab08dbecb 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -2201,6 +2201,9 @@ static int clk_core_set_rate_nolock(struct 
> clk_core *core,
>          if (!core)
>                  return 0;
> 
> +       if (req_rate == 0)
> +               return 0;
> +
>          rate = clk_core_req_round_rate_nolock(core, req_rate);
> 
>          /* bail early if nothing to do */
> --
> 
> I will soon grab the call stack and relevant clock topology show how the 
> rate is set to zero.

The most likely thing to happen is that clk_set_rate_range will call
clk_core_set_rate_nolock with clk_core->req_rate, and at the time
req_rate is at 0.

And I'm a bit puzzled at this point, the only reason I could spot for
req_rate to be at 0 is that it's an orphan clock that doesn't have its
parent yet, but during userspace init I'd expect all the clocks to have
been registered.

Can you check if that clock is still orphan?

Maxime