Re: [PATCH 1/2] dt-bindings: clk: Add binding for versal clocking wizard

Michal Simek
2022-10-04T11:05:34Z

On 10/4/22 13:00, Krzysztof Kozlowski wrote:
> On 03/10/2022 17:27, Michal Simek wrote:
>>>
>>> Exactly. The names xlnx,clocking-wizard and xlnx,clk-wizard-1.0 are
>>> therefore not specific enough and mixing different devices.
>>
>> And just to be clear these IPs can be combined with systems where the main cpu
>> can be Microblaze. I have also seen some vendors mixing RISC-V with Xilinx IPs.
>>
>> Please look below.
>>>
>>>> And because this is fpga world none is really describing programmable logic by
>>>> hand because it would take a look a lot of time. That's why I created long time
>>>> ago device-tree generator (DTG) which gets design data and based on it generate
>>>> device tree description. Newest version is available for example here.
>>>> https://github.com/Xilinx/device-tree-xlnx
>>>> There is also newer version called system device tree generato
>>>> https://github.com/Xilinx/system-device-tree-xlnx
>>>>
>>>> Because of this infrastructure user will all the time get proper compatible
>>>> string which is aligned with IP catalog.
>>>
>>> I don't think so. Let's skip for now "clk" and "clocking" differences
>>> and assume both are "clocking". You have then compatibles:
>>>
>>> xlnx,clocking-wizard and xlnx,clocking-wizard-1.0
>>>
>>> and you said these are entirely different blocks.
>>>
>>> There is no way this creates readable DTS.
>>
>> And I really thank you for this discussion to do it properly and have proper
>> compatible string and description for this block.
>>
>> Shubhrajyoti: please correct me if I am wrong.
>>
>> All Xilinx SOCs have programmable logic aligned with FPGAs. Zynq is based 28nm,
>> ZynqMP (Ultrascale MPSOC) is based on 16nm and Versal is based on 7nm.
>>
>> I think these clocking IPs are using low level primitives available in PL logic.
>> Which means there is connection to fpga/pl technology instead of SOC family and
>> main cpu.
>
> Then maybe the compatibles (and device names) should have that fpga/pl
> technology used to differentiate between them?

I am already trying to find out better generic description without mentioning
sizes.

>> It can be of course said that if this is ZynqMP SOC that IP A is used. The same
>> for Versal SOC. But for soft cores this can't be said.
>>
>> Would it be better to reflect PL technology in compatible string?
>
> Yes, although we might misunderstand what PL technology is. 28/16/7 nm
> is the size of transistor or the process. Even two different processes
> can use same type of technology, e.g. FinFET:
> https://en.wikipedia.org/wiki/14_nm_process
> https://en.wikipedia.org/wiki/10_nm_process
>
> You could have very similar (or even the same) designs done in 28 nm and
> 16 nm. Does it mean these are entirely different devices? Not
> necessarily... Maybe they are, maybe not, but is the size of process
> differentiating? I actually don't know what's there in 28/16/7, I am
> just saying that number alone might not mean different technology.
> Programming API could be the same, inputs/outputs could be the same.
> Just the size of transistor is different...

I agree. Will try to come up with better name without nm inside to uniquely
identify PL logic type.

Thanks,
Michal