Re: [PATCH 1/2] dt-bindings: clk: Add binding for versal clocking wizard

Michal Simek
2022-09-30T13:00:42Z

Hi Rob,

On 9/30/22 14:25, Rob Herring wrote:
> On Fri, Sep 30, 2022 at 3:04 AM Shubhrajyoti Datta
> <shubhrajyoti.datta@amd.com> wrote:
>>
>> The Clocking Wizard for Versal adaptive compute acceleration platforms
>> generates multiple configurable number of clock outputs.
>> Add device tree binding for Versal clocking wizard support.
>
> Really v1? I'm sure I heard of this wizard before.
>
> What about this?:
>
> drivers/staging/clocking-wizard/dt-binding.txt
>
> That needs to be moved out of staging rather than adding a 2nd one.

Let me clarify this. This is IP which is already moved out of staging.
Linux-next has these changes and waiting for MW to happen (already in clock tree).

And this is new IP. Not sure who has chosen similar name but this targets Xilinx
Versal SOCs. Origin one was targeting previous families.

>
>>
>> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
>> ---
>>
>> .../bindings/clock/xlnx,clk-wizard.yaml | 66 +++++++++++++++++++
>> 1 file changed, 66 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clk-wizard.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.yaml
>> new file mode 100644
>> index 000000000000..41a6f4bcaccd
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/xlnx,clk-wizard.yaml
>> @@ -0,0 +1,66 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/xlnx,clk-wizard.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Xilinx Versal clocking wizard
>> +
>> +maintainers:
>> + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
>> +
>> +description:
>> + The clocking wizard is a soft ip clocking block of Xilinx versal. The IP
>> + uses the input clock frequencies and generates the requested
>> + clock output.
>> +
>> +properties:
>> + compatible:
>> + const: xlnx,clk-wizard-1.0
>
> Where does 1.0 come from? A 1.0 always feels made up. This should be
> based on some IP versioning that's documented somewhere.

Soft IP catalog name with version:
xilinx.com:ip:clk_wizard:1.0

https://docs.xilinx.com/r/en-US/pg321-clocking-wizard/Introduction

Thanks,
Michal