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Thu, 23 Jan 2025 13:29:16 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50NDTFWc021185 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Jan 2025 13:29:15 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 23 Jan 2025 05:29:12 -0800 Date: Thu, 23 Jan 2025 18:59:08 +0530 From: Varadarajan Narayanan To: Manikanta Mylavarapu CC: , , , , , , Subject: Re: [PATCH] clk: qcom: ipq5424: fix software and hardware flow control error of UART Message-ID: References: <20250123111618.1048461-1-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250123111618.1048461-1-quic_mmanikan@quicinc.com> X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: tEv4nDBXFgDgKUwnP8x9fnWOBhQ2Fb0n X-Proofpoint-ORIG-GUID: tEv4nDBXFgDgKUwnP8x9fnWOBhQ2Fb0n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-23_06,2025-01-22_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 phishscore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 suspectscore=0 malwarescore=0 impostorscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501230100 On Thu, Jan 23, 2025 at 04:46:18PM +0530, Manikanta Mylavarapu wrote: > The UART’s software and hardware flow control are currently not > functioning correctly. > > For software flow control, the following error is encountered: > qcom_geni_serial 1a80000.serial: Couldn't find suitable > clock rate for 56000000, 3500000, 2500000, 1152000, 921600, 19200 > > During hardware flow control testing, a “Retry 0: Got ZCAN error” is > observed. > > To address these issues, update the UART frequency table to include all > supported frequencies according to the frequency plan. Would this need fixes tag? -Varada > > Signed-off-by: Manikanta Mylavarapu > --- > drivers/clk/qcom/gcc-ipq5424.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c > index d5b218b76e29..37b1a3ff8f4e 100644 > --- a/drivers/clk/qcom/gcc-ipq5424.c > +++ b/drivers/clk/qcom/gcc-ipq5424.c > @@ -592,13 +592,19 @@ static struct clk_rcg2 gcc_qupv3_spi1_clk_src = { > }; > > static const struct freq_tbl ftbl_gcc_qupv3_uart0_clk_src[] = { > - F(960000, P_XO, 10, 2, 5), > - F(4800000, P_XO, 5, 0, 0), > - F(9600000, P_XO, 2, 4, 5), > - F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), > + F(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625), > + F(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625), > + F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625), > F(24000000, P_XO, 1, 0, 0), > F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), > - F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), > + F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), > + F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), > + F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500), > + F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), > + F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), > + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), > + F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625), > + F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), > F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), > { } > }; > > -- > 2.34.1 >