Re: [PATCH 5/6] arm64: dts: renesas: r9a08g045: Add TSU node

Daniel Lezcano
2025-01-30T17:54:01Z

On 03/01/2025 17:38, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add TSU node along with thermal zones and keep it enabled in the SoC DTSI.
> The temperature reported by the TSU can only be read through channel 8 of
> the ADC. Therefore, enable the ADC by default.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
> arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 43 ++++++++++++++++++-
> .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 --
> 2 files changed, 42 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> index a9b98db9ef95..fd74138198a8 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> @@ -205,7 +205,6 @@ adc: adc@10058000 {
> #address-cells = <1>;
> #size-cells = <0>;
> #io-channel-cells = <1>;
> - status = "disabled";
>
> channel@0 {
> reg = <0>;
> @@ -244,6 +243,17 @@ channel@8 {
> };
> };
>
> + tsu: thermal@10059000 {
> + compatible = "renesas,r9a08g045-tsu";
> + reg = <0 0x10059000 0 0x1000>;
> + clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>;
> + resets = <&cpg R9A08G045_TSU_PRESETN>;
> + power-domains = <&cpg>;
> + #thermal-sensor-cells = <0>;
> + io-channels = <&adc 8>;
> + io-channel-names = "tsu";
> + };
> +
> vbattb: clock-controller@1005c000 {
> compatible = "renesas,r9a08g045-vbattb";
> reg = <0 0x1005c000 0 0x1000>;
> @@ -690,6 +700,37 @@ timer {
> "hyp-virt";
> };
>
> + thermal-zones {
> + cpu_thermal: cpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> + thermal-sensors = <&tsu>;
> + sustainable-power = <423>;
> +
> + cooling-maps {
> + map0 {
> + trip = <&target>;
> + cooling-device = <&cpu0 0 2>;
> + contribution = <1024>;
> + };
> + };
> +
> + trips {
> + sensor_crit: sensor-crit {
> + temperature = <125000>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> +
> + target: trip-point {
> + temperature = <100000>;
> + hysteresis = <1000>;
> + type = "passive";
> + };

1. As you specified the sustainable power, the power allocator would be
used. However, it needs an intermediate passive trip point before
reaching the mitigation because the governor has to collect data ahead
of the passive mitigation trip point in order to feed the PID loop. This
trip point is not bound to any cooling device

2. The mitigation temperature is set to 100°C. The MTBF decay factor of
the semi-conductor will be increased by more the 100x times during the
thermal episodes stress thus reducing its lifespan considerably if it
hits this temperature often (but I doubt with a single Cortex-A55).

3. It would make sense to add a 'hot' trip point so the user space can
take an action to reduce the thermal pressure before reaching the
critical temperature

4. IIUC, the CPU does not do voltage scaling but only frequency scaling,
right ? If it is the case, then it is even more true that the mitigation
trip point should be reduced because the frequency scaling only may not
suffice to provide a cooling effect

> + };
> + };
> + };
> +
> vbattb_xtal: vbattb-xtal {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> index ef12c1c462a7..041d256d7b79 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> @@ -102,10 +102,6 @@ x3_clk: x3-clock {
> };
> };
>
> -&adc {
> - status = "okay";
> -};
> -
> #if SW_CONFIG3 == SW_ON
> &eth0 {
> pinctrl-0 = <&eth0_pins>;

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