From: Jiri Pirko <jiri@resnulli.us>
To: Jakub Kicinski <kuba@kernel.org>
Cc: Paolo Abeni <pabeni@redhat.com>,
"Kubalewski, Arkadiusz" <arkadiusz.kubalewski@intel.com>,
Vadim Fedorenko <vadim.fedorenko@linux.dev>,
Vadim Fedorenko <vadfed@meta.com>,
Jonathan Lemon <jonathan.lemon@gmail.com>,
poros <poros@redhat.com>, mschmidt <mschmidt@redhat.com>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
linux-arm-kernel@lists.infradead.org,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"Olech, Milena" <milena.olech@intel.com>,
"Michalik, Michal" <michal.michalik@intel.com>
Subject: Re: [PATCH RFC v6 2/6] dpll: Add DPLL framework base functions
Date: Tue, 9 May 2023 17:21:42 +0200 [thread overview]
Message-ID: <ZFplBpF3etwRY5nv@nanopsycho> (raw)
In-Reply-To: <20230509075247.2df8f5aa@kernel.org>
Tue, May 09, 2023 at 04:52:47PM CEST, kuba@kernel.org wrote:
>On Tue, 9 May 2023 09:53:07 +0200 Jiri Pirko wrote:
>> >Yup. Even renaming EXT to something that's less.. relative :(
>>
>> Suggestion?
>
>Well, is an SMT socket on the board an EXT pin?
>Which is why I prefer PANEL.
Makes sense.
To speak code, we'll have:
/**
* enum dpll_pin_type - defines possible types of a pin, valid values for
* DPLL_A_PIN_TYPE attribute
* @DPLL_PIN_TYPE_UNSPEC: unspecified value
* @DPLL_PIN_TYPE_MUX: aggregates another layer of selectable pins
* @DPLL_PIN_TYPE_PANEL: physically facing user, for example on a front panel
* @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock
* @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator
* @DPLL_PIN_TYPE_GNSS: GNSS recovered clock
*/
enum dpll_pin_type {
DPLL_PIN_TYPE_UNSPEC,
DPLL_PIN_TYPE_MUX,
DPLL_PIN_TYPE_PANEL,
DPLL_PIN_TYPE_SYNCE_ETH_PORT,
DPLL_PIN_TYPE_INT_OSCILLATOR,
DPLL_PIN_TYPE_GNSS,
__DPLL_PIN_TYPE_MAX,
DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1)
};
>
>> >> Well sure, in case there is no "label" attr for the rest of the types.
>> >> Which I believe it is, for the ice implementation in this patchset.
>> >> Otherwise, there is no way to distinguish between the pins.
>> >> To have multiple attrs for label for multiple pin types does not make
>> >> any sense to me, that was my point.
>> >
>> >Come on, am I really this bad at explaining this?
>>
>> Or perhaps I'm just slow.
>>
>> >If we make a generic "label" attribute driver authors will pack
>> >everything they want to expose to the user into it, and then some.
>>
>> What's difference in generic label string attr and type specific label
>> string attr. What is stopping driver developers to pack crap in either
>> of these 2. Perhaps I'm missing something. Could you draw examples?
>>
>> >So we need attributes which will feel *obviously* *wrong* to abuse.
>>
>> Sure, I get what you say and agree. I'm just trying to find out the
>> actual attributes :)
>
>PANEL label must match the name on the panel. User can take the card
>into their hand, look at the front, and there should be a label/sticker/
>/engraving which matches exactly what the kernel reports.
>
>If the label is printed on the board it's a BOARD_LABEL, if it's the
>name of a trace in board docs it's a BOARD_TRACE, if it's a pin of
>the ASIC it's a PACKAGE_PIN.
>
>If it's none of those, or user does not have access to the detailed
>board / pinout - don't use the label.
To speak code, we'll have:
DPLL_A_PIN_PANEL_LABEL (string)
available always when attr[DPLL_A_PIN_TYPE] == DPLL_PIN_TYPE_PANEL
DPLL_A_PIN_BOARD_LABEL (string)
may be available for any type, optional
DPLL_A_PIN_BOARD_TRACE (string)
may be available for any type, optional
DPLL_A_PIN_PACKAGE_PIN (string)
may be available for any type, optional
Makes sense?
But this does not prevent driver developer to pack random crap in the
string anyway :/
next prev parent reply other threads:[~2023-05-09 15:21 UTC|newest]
Thread overview: 103+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-12 2:28 [PATCH RFC v6 0/6] Create common DPLL/clock configuration API Vadim Fedorenko
2023-03-12 2:28 ` [PATCH RFC v6 1/6] dpll: spec: Add Netlink spec in YAML Vadim Fedorenko
2023-03-14 14:44 ` Jiri Pirko
2023-03-16 13:15 ` Kubalewski, Arkadiusz
2023-03-16 13:45 ` Jiri Pirko
2023-03-16 15:19 ` Jiri Pirko
2023-03-17 0:53 ` Kubalewski, Arkadiusz
2023-03-17 10:07 ` Jiri Pirko
2023-03-17 0:52 ` Kubalewski, Arkadiusz
2023-03-17 10:05 ` Jiri Pirko
2023-03-17 14:29 ` Jiri Pirko
2023-03-17 15:14 ` Kubalewski, Arkadiusz
2023-03-17 16:20 ` Jiri Pirko
2023-03-17 18:22 ` Kubalewski, Arkadiusz
2023-03-20 8:10 ` Jiri Pirko
2023-03-21 4:05 ` Jakub Kicinski
2023-03-21 4:13 ` Jakub Kicinski
2023-03-21 4:20 ` Jakub Kicinski
2023-03-17 16:23 ` Jiri Pirko
2023-03-21 4:00 ` Jakub Kicinski
2023-03-17 16:53 ` Jiri Pirko
2023-03-17 18:50 ` Kubalewski, Arkadiusz
2023-03-12 2:28 ` [PATCH RFC v6 2/6] dpll: Add DPLL framework base functions Vadim Fedorenko
2023-03-13 16:21 ` Jiri Pirko
2023-03-13 22:59 ` Vadim Fedorenko
2023-03-14 9:21 ` Jiri Pirko
2023-03-14 17:50 ` Kubalewski, Arkadiusz
2023-03-15 9:22 ` Jiri Pirko
2023-03-16 12:31 ` Jiri Pirko
2023-03-28 15:22 ` Vadim Fedorenko
2023-04-01 12:49 ` Jiri Pirko
2023-04-03 18:18 ` Jakub Kicinski
2023-04-09 7:51 ` Jiri Pirko
[not found] ` <20230410153149.602c6bad@kernel.org>
2023-04-16 16:23 ` Jiri Pirko
2023-04-17 15:53 ` Vadim Fedorenko
[not found] ` <20230417124942.4305abfa@kernel.org>
[not found] ` <ZFDPaXlJainSOqmV@nanopsycho>
[not found] ` <20230502083244.19543d26@kernel.org>
2023-05-03 7:56 ` Jiri Pirko
2023-05-04 2:16 ` Jakub Kicinski
2023-05-04 11:00 ` Jiri Pirko
2023-05-04 11:14 ` Jiri Pirko
2023-05-04 16:04 ` Jakub Kicinski
2023-05-04 17:51 ` Jiri Pirko
2023-05-04 18:44 ` Jakub Kicinski
2023-05-05 10:41 ` Jiri Pirko
2023-05-05 15:35 ` Jakub Kicinski
2023-05-07 7:58 ` Jiri Pirko
2023-05-08 6:50 ` Paolo Abeni
2023-05-08 12:17 ` Jiri Pirko
2023-05-08 19:42 ` Jakub Kicinski
2023-05-09 7:53 ` Jiri Pirko
2023-05-09 14:52 ` Jakub Kicinski
2023-05-09 15:21 ` Jiri Pirko [this message]
2023-05-09 17:53 ` Jakub Kicinski
2023-05-10 6:17 ` Jiri Pirko
2023-03-14 16:43 ` Kubalewski, Arkadiusz
2023-03-15 12:14 ` Jiri Pirko
2023-03-14 9:30 ` Jiri Pirko
2023-03-14 15:45 ` Jiri Pirko
2023-03-14 18:35 ` Kubalewski, Arkadiusz
2023-03-15 14:43 ` Jiri Pirko
2023-03-15 15:29 ` Jiri Pirko
2023-03-16 12:20 ` Jiri Pirko
2023-03-16 12:37 ` Jiri Pirko
2023-03-16 13:53 ` Jiri Pirko
2023-03-16 16:16 ` Jiri Pirko
2023-03-17 16:21 ` Jiri Pirko
2023-03-20 10:24 ` Jiri Pirko
2023-03-21 13:34 ` Jiri Pirko
2023-03-23 11:18 ` Jiri Pirko
2023-03-24 9:29 ` Jiri Pirko
2023-03-12 2:28 ` [PATCH RFC v6 3/6] dpll: documentation on DPLL subsystem interface Vadim Fedorenko
2023-03-14 16:14 ` Jiri Pirko
2023-04-03 10:21 ` Kubalewski, Arkadiusz
2023-03-16 13:46 ` Jiri Pirko
2023-04-03 10:23 ` Kubalewski, Arkadiusz
2023-03-12 2:28 ` [PATCH RFC v6 4/6] ice: add admin commands to access cgu configuration Vadim Fedorenko
2023-03-12 2:28 ` [PATCH RFC v6 5/6] ice: implement dpll interface to control cgu Vadim Fedorenko
2023-03-12 2:28 ` [PATCH RFC v6 6/6] ptp_ocp: implement DPLL ops Vadim Fedorenko
2023-03-14 10:05 ` Jiri Pirko
2023-03-15 0:10 ` Vadim Fedorenko
2023-03-15 12:24 ` Jiri Pirko
2023-03-31 23:28 ` Vadim Fedorenko
2023-04-01 12:53 ` Jiri Pirko
2023-03-15 15:34 ` Jiri Pirko
2023-03-15 15:52 ` Vadim Fedorenko
2023-03-16 12:12 ` Jiri Pirko
2023-03-13 12:20 ` [PATCH RFC v6 0/6] Create common DPLL/clock configuration API Jiri Pirko
2023-03-13 15:33 ` Vadim Fedorenko
2023-03-13 16:22 ` Jiri Pirko
2023-03-13 16:31 ` Vadim Fedorenko
2023-03-17 16:10 ` Jiri Pirko
2023-03-18 5:01 ` Jakub Kicinski
2023-03-23 11:21 ` Jiri Pirko
2023-03-23 18:00 ` Vadim Fedorenko
2023-03-26 17:00 ` [patch dpll-rfc 0/7] dpll: initial patchset extension by mlx5 implementation Jiri Pirko
2023-03-26 17:00 ` [patch dpll-rfc 1/7] dpll: make ops function args const Jiri Pirko
2023-03-26 17:00 ` [patch dpll-rfc 2/7] dpll: allow to call device register multiple times Jiri Pirko
2023-03-26 17:00 ` [patch dpll-rfc 3/7] dpll: introduce a helper to get first dpll ref and use it Jiri Pirko
2023-03-26 17:00 ` [patch dpll-rfc 4/7] dpll: allow to call pin register multiple times Jiri Pirko
2023-03-26 17:00 ` [patch dpll-rfc 5/7] dpll: export dpll_pin_notify() Jiri Pirko
2023-03-26 17:00 ` [patch dpll-rfc 6/7] netdev: expose DPLL pin handle for netdevice Jiri Pirko
2023-03-26 17:00 ` [patch dpll-rfc 7/7] mlx5: Implement SyncE support using DPLL infrastructure Jiri Pirko
2023-03-28 16:36 ` [patch dpll-rfc 0/7] dpll: initial patchset extension by mlx5 implementation Vadim Fedorenko
2023-04-01 12:54 ` Jiri Pirko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ZFplBpF3etwRY5nv@nanopsycho \
--to=jiri@resnulli.us \
--cc=arkadiusz.kubalewski@intel.com \
--cc=jonathan.lemon@gmail.com \
--cc=kuba@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=michal.michalik@intel.com \
--cc=milena.olech@intel.com \
--cc=mschmidt@redhat.com \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
--cc=poros@redhat.com \
--cc=vadfed@meta.com \
--cc=vadim.fedorenko@linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).