Re: [PATCH v3 2/4] dt-bindings: clock: mediatek: add clock controllers of MT7988

Krzysztof Kozlowski
2023-12-06T10:21:52Z

On 06/12/2023 01:57, Daniel Golle wrote:
> Add various clock controllers found in the MT7988 SoC to existing
> bindings (if applicable) and add files for the new ethwarp, mcusys
> and xfi-pll clock controllers not previously present in any SoC.
>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
> v3:
> * move clock bindings to clock folder
> * drop ti,syscon-reset from bindings and example
> * merge mcusys with topckgen bindings
>
> v2:
> * dropped unused labels
> * add 'type: object' declaration for reset-controller found in new
> ethwarp controller and represented as ti,syscon-reset
> * rebase on top of
> "dt-bindings: arm: mediatek: move ethsys controller & convert to DT schema"
>
> .../arm/mediatek/mediatek,infracfg.yaml | 1 +
> .../bindings/clock/mediatek,apmixedsys.yaml | 1 +
> .../bindings/clock/mediatek,ethsys.yaml | 1 +
> .../clock/mediatek,mt7988-ethwarp.yaml | 49 +++++++++++++++++++
> .../clock/mediatek,mt7988-xfi-pll.yaml | 48 ++++++++++++++++++
> .../bindings/clock/mediatek,topckgen.yaml | 2 +
> .../bindings/net/pcs/mediatek,sgmiisys.yaml | 13 +++--
> 7 files changed, 112 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> index ea98043c6ba3d..230b5188a88db 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> @@ -30,6 +30,7 @@ properties:
> - mediatek,mt7629-infracfg
> - mediatek,mt7981-infracfg
> - mediatek,mt7986-infracfg
> + - mediatek,mt7988-infracfg
> - mediatek,mt8135-infracfg
> - mediatek,mt8167-infracfg
> - mediatek,mt8173-infracfg
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
> index 372c1d744bc27..685535846cbb7 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
> @@ -22,6 +22,7 @@ properties:
> - mediatek,mt7622-apmixedsys
> - mediatek,mt7981-apmixedsys
> - mediatek,mt7986-apmixedsys
> + - mediatek,mt7988-apmixedsys
> - mediatek,mt8135-apmixedsys
> - mediatek,mt8173-apmixedsys
> - mediatek,mt8516-apmixedsys
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
> index 94d42c8647777..f9cddacc2eae1 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
> @@ -22,6 +22,7 @@ properties:
> - mediatek,mt7629-ethsys
> - mediatek,mt7981-ethsys
> - mediatek,mt7986-ethsys
> + - mediatek,mt7988-ethsys
> - const: syscon
> - items:
> - const: mediatek,mt7623-ethsys
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
> new file mode 100644
> index 0000000000000..9b919a155eb13
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7988-ethwarp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT7988 ethwarp Controller
> +
> +maintainers:
> + - Daniel Golle <daniel@makrotopia.org>
> +
> +description:
> + The Mediatek MT7988 ethwarp controller provides clocks and resets for the
> + Ethernet related subsystems found the MT7988 SoC.
> + The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
> +
> +properties:
> + compatible:
> + items:
> + - const: mediatek,mt7988-ethwarp
> + - const: syscon
> + - const: simple-mfd

Why this is a simple MFD without children? Something is not right here.
Either this is not simple-mfd or this is not complete binding.

> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/reset/ti-syscon.h>
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clock-controller@15031000 {
> + compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
> + reg = <0 0x15031000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
> new file mode 100644
> index 0000000000000..fe5e3a70299fd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
> @@ -0,0 +1,48 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7988-xfi-pll.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT7988 XFI PLL Clock Controller
> +
> +maintainers:
> + - Daniel Golle <daniel@makrotopia.org>
> +
> +description:
> + The MediaTek XFI PLL controller provides the 156.25MHz clock for the
> + Ethernet SerDes PHY from the 40MHz top_xtal clock.
> +
> +properties:
> + compatible:
> + const: mediatek,mt7988-xfi-pll
> +
> + reg:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - resets
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + clock-controller@11f40000 {
> + compatible = "mediatek,mt7988-xfi-pll";
> + reg = <0 0x11f40000 0 0x1000>;
> + resets = <&watchdog 16>;
> + #clock-cells = <1>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
> index 6d087ded7437a..bdf3b55bd56fd 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
> @@ -37,6 +37,8 @@ properties:
> - mediatek,mt7629-topckgen
> - mediatek,mt7981-topckgen
> - mediatek,mt7986-topckgen
> + - mediatek,mt7988-mcusys
> + - mediatek,mt7988-topckgen
> - mediatek,mt8167-topckgen
> - mediatek,mt8183-topckgen
> - const: syscon
> diff --git a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
> index 66a95191bd776..68632cda334bd 100644
> --- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
> +++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
> @@ -15,15 +15,22 @@ description:
>
> properties:
> compatible:
> - items:
> - - enum:
> + oneOf:
> + - items:
> + - enum:

It does not look like you tested the bindings, at least after quick
look. Please run `make dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Maybe you need to update your dtschema and yamllint.

Best regards,
Krzysztof