On Tue, Jan 30, 2024 at 10:47:49AM +0100, Geert Uytterhoeven wrote:
> Fix a typo in the name of the module clock for the second PCIe channel.
> 
> Fixes: 5ab16198b431ca48 ("clk: renesas: r8a779g0: Add PCIe clocks")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>