* [PATCH] clk:sophgo:clk-cv18xx-pll: fix unitialized u32 variable
@ 2024-11-13 2:02 Ragavendra
2024-11-13 23:36 ` Chen Wang
0 siblings, 1 reply; 3+ messages in thread
From: Ragavendra @ 2024-11-13 2:02 UTC (permalink / raw)
To: mturquette, sboyd, unicorn_wang, inochiama
Cc: linux-clk, linux-kernel, Ragavendra
Initializing the val variable of type u32 as it was not initialized.
Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
Signed-off-by: Ragavendra Nagraj <ragavendra.bn@gmail.com>
---
drivers/clk/sophgo/clk-cv18xx-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c
index 29e24098bf5f..04a0419cab4e 100644
--- a/drivers/clk/sophgo/clk-cv18xx-pll.c
+++ b/drivers/clk/sophgo/clk-cv18xx-pll.c
@@ -87,7 +87,7 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,
static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
- u32 val;
+ u32 val = 0;
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
return ipll_find_rate(pll->pll_limit, req->best_parent_rate,
--
2.46.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] clk:sophgo:clk-cv18xx-pll: fix unitialized u32 variable
2024-11-13 2:02 [PATCH] clk:sophgo:clk-cv18xx-pll: fix unitialized u32 variable Ragavendra
@ 2024-11-13 23:36 ` Chen Wang
2024-11-14 20:04 ` Ragavendra B.N.
0 siblings, 1 reply; 3+ messages in thread
From: Chen Wang @ 2024-11-13 23:36 UTC (permalink / raw)
To: Ragavendra, mturquette, sboyd, inochiama; +Cc: linux-clk, linux-kernel
Hi, Ragavendra,
This patch should be dropped, right? I see a new patch
https://lore.kernel.org/linux-clk/20241113184617.3745423-1-ragavendra.bn@gmail.com/
should have covered this.
Suggest you reply this patch email and declare the dropping to avoid
confusion.
On 2024/11/13 10:02, Ragavendra wrote:
> Initializing the val variable of type u32 as it was not initialized.
>
> Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
> Signed-off-by: Ragavendra Nagraj <ragavendra.bn@gmail.com>
> ---
> drivers/clk/sophgo/clk-cv18xx-pll.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c
> index 29e24098bf5f..04a0419cab4e 100644
> --- a/drivers/clk/sophgo/clk-cv18xx-pll.c
> +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c
> @@ -87,7 +87,7 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,
>
> static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
> {
> - u32 val;
> + u32 val = 0;
> struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
>
> return ipll_find_rate(pll->pll_limit, req->best_parent_rate,
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] clk:sophgo:clk-cv18xx-pll: fix unitialized u32 variable
2024-11-13 23:36 ` Chen Wang
@ 2024-11-14 20:04 ` Ragavendra B.N.
0 siblings, 0 replies; 3+ messages in thread
From: Ragavendra B.N. @ 2024-11-14 20:04 UTC (permalink / raw)
To: Chen Wang, mturquette, sboyd, inochiama, ragavendra.bn
Cc: linux-clk, linux-kernel
On Thu, Nov 14, 2024 at 07:36:21AM +0800, Chen Wang wrote:
> Hi, Ragavendra,
>
> This patch should be dropped, right? I see a new patch https://lore.kernel.org/linux-clk/20241113184617.3745423-1-ragavendra.bn@gmail.com/
> should have covered this.
>
> Suggest you reply this patch email and declare the dropping to avoid
> confusion.
>
> On 2024/11/13 10:02, Ragavendra wrote:
> > Initializing the val variable of type u32 as it was not initialized.
> >
> > Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
> > Signed-off-by: Ragavendra Nagraj <ragavendra.bn@gmail.com>
> > ---
> > drivers/clk/sophgo/clk-cv18xx-pll.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c
> > index 29e24098bf5f..04a0419cab4e 100644
> > --- a/drivers/clk/sophgo/clk-cv18xx-pll.c
> > +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c
> > @@ -87,7 +87,7 @@ static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,
> > static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
> > {
> > - u32 val;
> > + u32 val = 0;
> > struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
> > return ipll_find_rate(pll->pll_limit, req->best_parent_rate,
hi Chen,
You are correct, please drop this patch email.
--
Yours sincerely,
Ragavendra N
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-11-13 2:02 [PATCH] clk:sophgo:clk-cv18xx-pll: fix unitialized u32 variable Ragavendra
2024-11-13 23:36 ` Chen Wang
2024-11-14 20:04 ` Ragavendra B.N.
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