From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Subject: Re: [linux-sunxi] [PATCH v4 4/9] pinctrl: sunxi: add support for the Allwinner H6 main pin controller To: icenowy@aosc.io, Rob Herring , Maxime Ripard , Chen-Yu Tsai , Linus Walleij Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com References: <20180316140215.28663-1-icenowy@aosc.io> <20180316140215.28663-5-icenowy@aosc.io> From: Andre Przywara Message-ID: Date: Fri, 16 Mar 2018 17:07:28 +0000 MIME-Version: 1.0 In-Reply-To: <20180316140215.28663-5-icenowy@aosc.io> Content-Type: text/plain; charset=utf-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: Hi, On 16/03/18 14:02, Icenowy Zheng wrote: > The Allwinner H6 SoC has two pin controllers, one main controller > (called CPUX-PORT in user manual) and one controller in CPUs power > domain (called CPUS-PORT in user manual). > > This commit introduces support for the main pin controller on H6. > > The pin bank A and B are not wired out and hidden from the SoC's > documents, however it's shown that the "ATE" (an AC200 chip > co-packaged with the H6 die) is connected to the main SoC die via these > pin banks. The information about these banks is just copied from the BSP > pinctrl driver, but re-formatted to fit the mainline pinctrl driver > format. The GPIO functions are dropped, as they're impossible to use -- > except a GPIO&IRQ only pin (PB20) which might be the IRQ of ATE. > > Signed-off-by: Icenowy Zheng > Acked-by: Rob Herring As mentioned before, I checked every single pin against the manual and this looks correct to me. Reviewed-by: Andre Przywara Thanks! Andre.