Re: [PATCH 7/8] arm64: dts: qcom: add IPQ5424 SoC and rdp466 board support

Sricharan Ramabadhran
2024-09-23T09:27:52Z

On 9/19/2024 6:00 PM, Krzysztof Kozlowski wrote:
[..]

>> +
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> new file mode 100644
>> index 000000000000..b6c08fac9482
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> @@ -0,0 +1,294 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * IPQ5424 device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
>> +#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + interrupt-parent = <&intc>;
>> +
>> + clocks {
>> + xo_board: xo-board-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + sleep_clk: sleep-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>> + cpus: cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + CPU0: cpu@0 {
>
> Lowercase labels please.
>
> I am in process of fixing it everywhere.
>
ok

>> + device_type = "cpu";
>> + compatible = "arm,cortex-a55";
>> + reg = <0x0>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_0>;
>> + L2_0: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + L3_0: l3-cache {
>> + compatible = "cache";
>> + cache-level = <3>;
>> + cache-unified;
>> + };
>> + };
>> + };
>> +
>> + CPU1: cpu@100 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a55";
>> + enable-method = "psci";
>> + reg = <0x100>;
>> + next-level-cache = <&L2_100>;
>> + L2_100: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU2: cpu@200 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a55";
>> + enable-method = "psci";
>> + reg = <0x200>;
>> + next-level-cache = <&L2_200>;
>> + L2_200: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU3: cpu@300 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a55";
>> + enable-method = "psci";
>> + reg = <0x300>;
>> + next-level-cache = <&L2_300>;
>> + L2_300: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> + };
>> +
>> + memory@80000000 {
>> + device_type = "memory";
>> + /* We expect the bootloader to fill in the size */
>> + reg = <0x0 0x80000000 0x0 0x0>;
>> + };
>> +
>> + pmu {
>
> pmu-a55
>
ok

>> + compatible = "arm,cortex-a55-pmu";
>> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> + };
>> +
>> + pmu-v7 {
>
> pmu-a7 but... where is the A7 CPU?
>
oops, by mistake. Renamed to a55 above, but missed deleting here.

>> + compatible = "arm,cortex-a7-pmu";
>> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>
> Same interrupts? Huh?
>
will be removed.

>> + };
>> +
>> + dsu-pmu {
>
> pmu-dsu?
>
ok

>> + compatible = "arm,dsu-pmu";
>> + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
>> + cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
>> + status = "okay";
>
> Drop
>
ok

>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-1.0";
>> + method = "smc";
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + tz@8a600000 {
>> + reg = <0x0 0x8a600000 0x0 0x200000>;
>> + no-map;
>> + };
>> + };
>> +
>> + soc@0 {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0 0 0 0 0x10 0>;
>> +
>> + tlmm: pinctrl@1000000 {
>> + compatible = "qcom,ipq5424-tlmm";
>> + reg = <0 0x01000000 0 0x300000>;
>> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + gpio-ranges = <&tlmm 0 0 50>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + uart1_pins: uart1-state {
>> + pins = "gpio43", "gpio44";
>> + function = "uart1";
>> + drive-strength = <8>;
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + gcc: clock-controller@1800000 {
>> + compatible = "qcom,ipq5424-gcc";
>> + reg = <0 0x01800000 0 0x40000>;
>> + clocks = <&xo_board>,
>> + <&sleep_clk>,
>> + <0>,
>> + <0>,
>> + <0>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #interconnect-cells = <1>;
>> + };
>> +
>> + qupv3: geniqup@1ac0000 {
>> + compatible = "qcom,geni-se-qup";
>> + reg = <0 0x01ac0000 0 0x2000>;
>> + clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
>> + <&gcc GCC_QUPV3_AHB_SLV_CLK>;
>> + clock-names = "m-ahb", "s-ahb";
>> + ranges;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + status = "okay";
>
> Please do not upstream your downstream code...
>
Sure, will remove here and below place

Regards,
Sricharan

>> +
>> + uart1: serial@1a84000 {
>> + compatible = "qcom,geni-debug-uart";
>> + reg = <0 0x01a84000 0 0x4000>;
>> + clocks = <&gcc GCC_QUPV3_UART1_CLK>;
>> + clock-names = "se";
>> + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "okay";
>
> Work on upstream instead.
>
>> + };
>> + };
>> +
>
>
> Best regards,
> Krzysztof
>