Re: [PATCH v5 07/19] clk: qcom: dispcc-qcm2290: Switch to DT index based clk lookup

[Imran Shaik <imran.shaik@oss.qualcomm.com>]

On 03-07-2026 12:45 pm, Konrad Dybcio wrote:
> On 7/2/26 8:31 PM, Imran Shaik wrote:
>> Update the QCM2290 DISPCC driver to use the DT index based parent clock
>> lookup to align with the latest convention. While updating the parent data,
>> fix the MDSS MDP clock source parent to use gcc_disp_gpll0_div_clk_src
>> instead of gcc_disp_gpll0_clk_src. This parent is currently unused by the
>> frequency tables, but should be corrected to match the hardware clock plan.
> 
> That change is invalid according to the agatti clock docs -
> DISP_CC_MDSS_MDP_CLK_SRC RCG leg 4 takes GPLL0_OUT_MAIN as
> an input
> 

The HW clock plan naming convention is slightly misleading. Though the 
DISPCC HW clock plan specifies the GPLL0_OUT_MAIN, it is actually 
sourced from external gcc_disp_gpll0_div_clk_src(300MHz) clock.

The above mapping is correctly handled for the mdss_ahb_clk_src already. 
But it is incorrect for the mdss_mdp_clk_src, hence fixing it now.

I will split this fix to a separate patch as Dmitry suggested in the 
other thread.

Thanks,
Imran