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[97.120.122.6]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22e15232797sm10306915ad.240.2025.05.02.10.35.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 May 2025 10:35:49 -0700 (PDT) Date: Fri, 2 May 2025 10:35:48 -0700 From: Drew Fustini To: Michal Wilczynski , Stephen Boyd Cc: Stephen Boyd , mturquette@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, guoren@kernel.org, wefu@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, jszhang@kernel.org, p.zabel@pengutronix.de, m.szyprowski@samsung.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v7 3/3] riscv: dts: thead: Add device tree VO clock controller Message-ID: References: <20250403094425.876981-1-m.wilczynski@samsung.com> <20250403094425.876981-4-m.wilczynski@samsung.com> <17d69810-9d1c-4dd9-bf8a-408196668d7b@samsung.com> <9ce45e7c1769a25ea1abfaeac9aefcfb@kernel.org> <475c9a27-e1e8-4245-9ca0-74c9ed663920@samsung.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <475c9a27-e1e8-4245-9ca0-74c9ed663920@samsung.com> On Wed, Apr 30, 2025 at 09:52:29AM +0200, Michal Wilczynski wrote: > > > On 4/30/25 00:29, Stephen Boyd wrote: > > Quoting Michal Wilczynski (2025-04-07 08:30:43) > >> On 4/5/25 01:16, Drew Fustini wrote: > >>>> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > >>>> index 527336417765..d4cba0713cab 100644 > >>>> --- a/arch/riscv/boot/dts/thead/th1520.dtsi > >>>> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > >>>> @@ -489,6 +489,13 @@ clk: clock-controller@ffef010000 { > >>>> #clock-cells = <1>; > >>>> }; > >>>> > >>>> + clk_vo: clock-controller@ffef528050 { > >>>> + compatible = "thead,th1520-clk-vo"; > >>>> + reg = <0xff 0xef528050 0x0 0xfb0>; > >>> > >>> Thanks for your patch. It is great to have more of the clocks supported > >>> upstream. > >>> > >>> The TH1520 System User Manual shows 0xFF_EF52_8000 for VO_SUBSYS on page > >>> 205. Is there a reason you decided to use 0xFF_EF52_8050 as the base? > >>> > >>> I see on page 213 that the first register for VO_SUBSYS starts with > >>> VOSYS_CLK_GATE at offset 0x50. I figure you did this to have the > >>> CCU_GATE macros use offset of 0x0 instead 0x50. > >>> > >>> I kind of think the reg property using the actual base address > >>> (0xFF_EF52_8000) makes more sense as that's a closer match to the tables > >>> in the manual. But I don't have a strong preference if you think think > >>> using 0xef528050 makes the CCU_GATE macros easier to read. > >> > >> Thank you for your comment. > >> > >> This was discussed some time ago. The main issue was that the address > >> space was fragmented between clocks and resets. Initially, I proposed > >> using syscon as a way to abstract this, but the idea wasn't particularly > >> well received. > >> > >> So at the start of the 0xFF_EF52_8000 there is a reset register GPU_RST_CFG > >> I need for resetting the GPU. > >> > >> For reference, here's the earlier discussion: [1] > >> > >> [1] - https://lore.kernel.org/all/1b05b11b2a8287c0ff4b6bdd079988c7.sboyd@kernel.org/ > >> > > > > In that email I said you should have one node > > clock-controller@ffef528000. Why did 0x50 get added to the address? > > Hi Stephen, > In the v2 version of the patchset, there was no reset controller yet, so > I thought your comment was made referring to that earlier version. > This representation clearly describes the hardware correctly, which is > the requirement for the Device Tree. > > The manual, in section 5.4.1.6 VO_SUBSYS, describes the reset registers > starting at 0xFF_EF52_8000: > > GPU_RST_CFG 0x00 > DPU_RST_CFG 0x04 > MIPI_DSI0_RST_CFG 0x8 > MIPI_DSI1_RST_CFG 0xc > HDMI_RST_CFG 0x14 > AXI4_VO_DW_AXI 0x18 > X2H_X4_VOSYS_DW_AXI_X2H 0x20 > > And the clock registers for VO_SUBSYS, manual section 4.4.1.6 start at offset 0x50: > VOSYS_CLK_GATE 0x50 > VOSYS_CLK_GATE1 0x54 > VOSYS_DPU_CCLK_CFG0 0x64 > TEST_CLK_FREQ_STAT 0xc4 > TEST_CLK_CFG 0xc8 > > So I considered this back then and thought it was appropriate to divide > it into two nodes, as the reset node wasn't being considered at that > time. > > When looking for the reference [1], I didn't notice if you corrected > yourself later, but I do remember considering the single-node approach > at the time. > > > > > Best regards, > -- > Michal Wilczynski I chatted with Stephen on irc about setting up a thead clk branch and sending pull requests to Stephen. Stephen - are there changes in this series that you want to see in order to give your Reviewed-by? Thanks, Drew