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[97.120.245.201]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b2fe168987esm5294629a12.57.2025.06.15.11.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jun 2025 11:03:30 -0700 (PDT) Date: Sun, 15 Jun 2025 11:03:28 -0700 From: Drew Fustini To: Michal Wilczynski Cc: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?iso-8859-1?Q?Bj=F6rn?= Roy Baron , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Benno Lossin , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v2 3/7] clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSED Message-ID: References: <20250610-rust-next-pwm-working-fan-for-sending-v2-0-753e2955f110@samsung.com> <20250610-rust-next-pwm-working-fan-for-sending-v2-3-753e2955f110@samsung.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250610-rust-next-pwm-working-fan-for-sending-v2-3-753e2955f110@samsung.com> On Tue, Jun 10, 2025 at 02:52:51PM +0200, Michal Wilczynski wrote: > Probing peripherals in the AON and PERI domains, such as the PVT thermal > sensor and the PWM controller, can lead to boot hangs or unresponsive > devices on the LPi4A board. The root cause is that their parent bus > clocks ('CLK_CPU2AON_X2H' and the 'CLK_PERISYS_APB' clocks) are > automatically gated by the kernel's power-saving mechanisms when the bus > is perceived as idle. > > Alternative solutions were investigated, including modeling the parent > bus in the Device Tree with 'simple-pm-bus' or refactoring the clock > driver's parentage. The 'simple-pm-bus' approach is not viable due to > the lack of defined bus address ranges in the hardware manual and its > creation of improper dependencies on the 'pm_runtime' API for consumer > drivers. > > Therefore, applying the'`CLK_IGNORE_UNUSED' flag directly to the > essential bus clocks is the most direct and targeted fix. This prevents > the kernel from auto-gating these buses and ensures peripherals remain > accessible. > > This change fixes the boot hang associated with the PVT sensor and > resolves the functional issues with the PWM controller. > > [1] - https://lore.kernel.org/all/9e8a12db-236d-474c-b110-b3be96edf057@samsung.com/ > > Signed-off-by: Michal Wilczynski > --- > drivers/clk/thead/clk-th1520-ap.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c > index ebfb1d59401d05443716eb0029403b01775e8f73..cf7f6bd428a0faa4611b3fc61edbbc6690e565d9 100644 > --- a/drivers/clk/thead/clk-th1520-ap.c > +++ b/drivers/clk/thead/clk-th1520-ap.c > @@ -792,11 +792,12 @@ static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x", axi4_cpusys2_ac > 0x134, BIT(8), 0); > static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys", axi4_cpusys2_aclk_pd, > 0x134, BIT(7), 0); > -static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_pd, 0x138, BIT(8), 0); > +static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", axi_aclk_pd, > + 0x138, BIT(8), CLK_IGNORE_UNUSED); > static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h", axi4_cpusys2_aclk_pd, > 0x140, BIT(9), CLK_IGNORE_UNUSED); > static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-apb1-hclk", perisys_ahb_hclk_pd, > - 0x150, BIT(9), 0); > + 0x150, BIT(9), CLK_IGNORE_UNUSED); > static CCU_GATE(CLK_PERISYS_APB2_HCLK, perisys_apb2_hclk, "perisys-apb2-hclk", perisys_ahb_hclk_pd, > 0x150, BIT(10), CLK_IGNORE_UNUSED); > static CCU_GATE(CLK_PERISYS_APB3_HCLK, perisys_apb3_hclk, "perisys-apb3-hclk", perisys_ahb_hclk_pd, > > -- > 2.34.1 > I'm okay with fixing it this way for now and revisiting the parent relationships later. Reviewed-by: Drew Fustini