Re: [PATCH 16/20] PCI: rockchip: switch to HWORD_UPDATE* macros

Yury Norov
2025-06-12T19:52:12Z

On Thu, Jun 12, 2025 at 02:37:28PM -0500, Bjorn Helgaas wrote:
> On Thu, Jun 12, 2025 at 08:56:18PM +0200, Nicolas Frattaroli wrote:
> > The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
> > drivers that use constant masks.
> >
> > The Rockchip PCI driver, like many other Rockchip drivers, has its very
> > own definition of HIWORD_UPDATE.
> >
> > Remove it, and replace its usage with either HWORD_UPDATE, or two new
> > header local macros for setting/clearing a bit with the high mask, which
> > use HWORD_UPDATE_CONST internally. In the process, ENCODE_LANES needed
> > to be adjusted, as HWORD_UPDATE* shifts the value for us.
> >
> > That this is equivalent was verified by first making all HWORD_UPDATE
> > instances HWORD_UPDATE_CONST, then doing a static_assert() comparing it
> > to the old macro (and for those with parameters, static_asserting for
> > the full range of possible values with the old encode macro).
> >
> > What we get out of this is compile time error checking to make sure the
> > value actually fits in the mask, and that the mask fits in the register,
> > and also generally less icky code that writes shifted values when it
> > actually just meant to set and clear a handful of bits.
> >
> > Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
>
> Looks good to me. I assume you want to merge these via a non-PCI tree
> since this depends on patch 01/20. PCI subject convention would
> capitalize "Switch":

Hi,

I'd like to take patch #1 and the explicitly acked following patches in
my bitmap-for-next.Those who would prefer to move the material in their
per-driver branches (like net, as mentioned by Andrew Lunn) can wait
till the end of next merge window, and then apply the patches cleanly.

Thanks,
Yury

> PCI: rockchip: Switch to HWORD_UPDATE* macros
>
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>
> > ---
> > drivers/pci/controller/pcie-rockchip.h | 35 +++++++++++++++++-----------------
> > 1 file changed, 18 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
> > index 5864a20323f21a004bfee4ac6d3a1328c4ab4d8a..5f2e45f062d94cd75983f7ad0c5b708e5b4cfb6f 100644
> > --- a/drivers/pci/controller/pcie-rockchip.h
> > +++ b/drivers/pci/controller/pcie-rockchip.h
> > @@ -11,6 +11,7 @@
> > #ifndef _PCIE_ROCKCHIP_H
> > #define _PCIE_ROCKCHIP_H
> >
> > +#include <linux/bitfield.h>
> > #include <linux/clk.h>
> > #include <linux/kernel.h>
> > #include <linux/pci.h>
> > @@ -21,10 +22,10 @@
> > * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
> > * bits. This allows atomic updates of the register without locking.
> > */
> > -#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
> > -#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
> > +#define HWORD_SET_BIT(val) (HWORD_UPDATE_CONST((val), 1))
> > +#define HWORD_CLR_BIT(val) (HWORD_UPDATE_CONST((val), 0))
> >
> > -#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
> > +#define ENCODE_LANES(x) ((((x) >> 1) & 3))
> > #define MAX_LANE_NUM 4
> > #define MAX_REGION_LIMIT 32
> > #define MIN_EP_APERTURE 28
> > @@ -32,21 +33,21 @@
> >
> > #define PCIE_CLIENT_BASE 0x0
> > #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
> > -#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
> > -#define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0)
> > -#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
> > -#define PCIE_CLIENT_LINK_TRAIN_DISABLE HIWORD_UPDATE(0x0002, 0)
> > -#define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
> > -#define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
> > -#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
> > -#define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0)
> > -#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
> > -#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
> > +#define PCIE_CLIENT_CONF_ENABLE HWORD_SET_BIT(0x0001)
> > +#define PCIE_CLIENT_CONF_DISABLE HWORD_CLR_BIT(0x0001)
> > +#define PCIE_CLIENT_LINK_TRAIN_ENABLE HWORD_SET_BIT(0x0002)
> > +#define PCIE_CLIENT_LINK_TRAIN_DISABLE HWORD_CLR_BIT(0x0002)
> > +#define PCIE_CLIENT_ARI_ENABLE HWORD_SET_BIT(0x0008)
> > +#define PCIE_CLIENT_CONF_LANE_NUM(x) HWORD_UPDATE(0x0030, ENCODE_LANES(x))
> > +#define PCIE_CLIENT_MODE_RC HWORD_SET_BIT(0x0040)
> > +#define PCIE_CLIENT_MODE_EP HWORD_CLR_BIT(0x0040)
> > +#define PCIE_CLIENT_GEN_SEL_1 HWORD_CLR_BIT(0x0080)
> > +#define PCIE_CLIENT_GEN_SEL_2 HWORD_SET_BIT(0x0080)
> > #define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c)
> > -#define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002)
> > -#define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0)
> > -#define PCIE_CLIENT_INT_PEND_ST_PEND HIWORD_UPDATE_BIT(0x0001)
> > -#define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0)
> > +#define PCIE_CLIENT_INT_IN_ASSERT HWORD_SET_BIT(0x0002)
> > +#define PCIE_CLIENT_INT_IN_DEASSERT HWORD_CLR_BIT(0x0002)
> > +#define PCIE_CLIENT_INT_PEND_ST_PEND HWORD_SET_BIT(0x0001)
> > +#define PCIE_CLIENT_INT_PEND_ST_NORMAL HWORD_CLR_BIT(0x0001)
> > #define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20)
> > #define PCIE_CLIENT_PHY_ST BIT(12)
> > #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c)
> >
> > --
> > 2.49.0
> >