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Wed, 30 Jul 2025 04:25:11 -0700 (PDT) Date: Wed, 30 Jul 2025 14:25:09 +0300 From: Abel Vesa To: Taniya Das Cc: kernel@oss.qualcomm.com, Pankaj Patil , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 3/7] clk: qcom: Add TCSR clock driver for Glymur Message-ID: References: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-0-227cfe5c8ef4@oss.qualcomm.com> <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-3-227cfe5c8ef4@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-3-227cfe5c8ef4@oss.qualcomm.com> On 25-07-29 11:12:37, Taniya Das wrote: > Add a clock driver for the TCSR clock controller found on Glymur, which > provides refclks for PCIE, USB, and UFS. > > Signed-off-by: Taniya Das > --- > drivers/clk/qcom/Kconfig | 8 ++ > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/tcsrcc-glymur.c | 257 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 266 insertions(+) > [...] > + > +static struct clk_branch tcsr_edp_clkref_en = { > + .halt_reg = 0x1c, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x1c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "tcsr_edp_clkref_en", > + .ops = &clk_branch2_ops, As discussed off-list, these clocks need to have the bi_tcxo as parent. Otherwise, as far as the CCF is concerned these clocks will have rate 0, which is obviously not the case. Bringing this here since there is a disconnect between X Elite and Glymur w.r.t this now.